UART Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: 4ec736f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	6.890s	6.201ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.680s	91.761us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.460s	14.091us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.980s	60.300us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.790s	122.116us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.650s	32.529us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.460s	14.091us	1	1	100.00
		uart_csr_aliasing	1.790s	122.116us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	28.950s	41.373ms	1	1	100.00
V2	parity	uart_smoke	6.890s	6.201ms	1	1	100.00
		uart_tx_rx	28.950s	41.373ms	1	1	100.00
V2	parity_error	uart_intr	1.732m	116.634ms	1	1	100.00
		uart_rx_parity_err	16.400s	47.571ms	1	1	100.00
V2	watermark	uart_tx_rx	28.950s	41.373ms	1	1	100.00
		uart_intr	1.732m	116.634ms	1	1	100.00
V2	fifo_full	uart_fifo_full	20.080s	30.556ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	16.900s	27.270ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	48.740s	147.646ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.732m	116.634ms	1	1	100.00
V2	rx_break_err	uart_intr	1.732m	116.634ms	1	1	100.00
V2	rx_timeout	uart_intr	1.732m	116.634ms	1	1	100.00
V2	perf	uart_perf	2.401m	4.433ms	1	1	100.00
V2	sys_loopback	uart_loopback	7.180s	9.586ms	1	1	100.00
V2	line_loopback	uart_loopback	7.180s	9.586ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.326m	116.343ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.890s	4.153ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	14.000s	6.074ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.540s	5.899ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	8.607m	97.476ms	1	1	100.00
V2	stress_all	uart_stress_all	3.557m	46.834ms	1	1	100.00
V2	alert_test	uart_alert_test	1.890s	83.040us	1	1	100.00
V2	intr_test	uart_intr_test	1.450s	11.706us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.860s	164.835us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.860s	164.835us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.680s	91.761us	1	1	100.00
		uart_csr_rw	1.460s	14.091us	1	1	100.00
		uart_csr_aliasing	1.790s	122.116us	1	1	100.00
		uart_same_csr_outstanding	1.540s	55.716us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.680s	91.761us	1	1	100.00
		uart_csr_rw	1.460s	14.091us	1	1	100.00
		uart_csr_aliasing	1.790s	122.116us	1	1	100.00
		uart_same_csr_outstanding	1.540s	55.716us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.910s	367.308us	1	1	100.00
		uart_tl_intg_err	1.990s	79.711us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.990s	79.711us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	41.670s	7.101ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.31617671446951604286690398882149979870479500053451043238208366642288063102442
      Line 74, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 40641725972 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 40641745972 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 40641845972 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 40663285972 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 40663285972 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1