CHIP Simulation Results

Thursday June 12 2025 18:43:49 UTC

GitHub Revision: `4ec736f`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.097m	2.972ms	1	1	100.00
		chip_sw_example_rom	1.060m	2.756ms	1	1	100.00
		chip_sw_example_manufacturer	1.407m	3.018ms	1	1	100.00
		chip_sw_example_concurrency	2.153m	2.883ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	4.170m	6.126ms	1	1	100.00
V1	csr_rw	chip_csr_rw	4.819m	5.468ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.220m	5.886ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.088h	38.706ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	51.810s	2.885ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.088h	38.706ms	1	1	100.00
		chip_csr_rw	4.819m	5.468ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.850s	49.849us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.755m	3.444ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.755m	3.444ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.755m	3.444ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.321m	4.650ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.321m	4.650ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.281m	4.018ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	4.934m	3.709ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.174m	3.873ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	14.804m	7.647ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	6.431m	5.043ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.146m	8.602ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.814m	4.836ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.814m	4.836ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.020m	2.866ms	0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.078m	4.951ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.682m	3.026ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	3.561m	4.197ms	1	1	100.00
		chip_tap_straps_testunlock0	5.521m	6.051ms	1	1	100.00
		chip_tap_straps_rma	1.176m	2.673ms	1	1	100.00
		chip_tap_straps_prod	1.531m	2.779ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.901m	2.633ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.768m	9.514ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.850m	5.387ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.850m	5.387ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.761m	7.230ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	16.590m	12.857ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.505m	3.940ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.309m	6.165ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.423m	18.376ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.825m	3.416ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.591m	5.854ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.600m	2.385ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.846m	13.918ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.962m	2.445ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.508m	4.770ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.106m	3.230ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.477m	3.396ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	10.126m	8.868ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.463m	5.435ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.106m	2.160ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	5.463m	5.435ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.256m	2.838ms	1	1	100.00
		chip_sw_aes_smoketest	2.121m	2.846ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.319m	3.026ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.268m	2.943ms	1	1	100.00
		chip_sw_csrng_smoketest	1.899m	2.455ms	1	1	100.00
		chip_sw_entropy_src_smoketest	5.031m	3.899ms	1	1	100.00
		chip_sw_gpio_smoketest	2.318m	2.918ms	1	1	100.00
		chip_sw_hmac_smoketest	2.359m	2.480ms	1	1	100.00
		chip_sw_kmac_smoketest	2.665m	2.550ms	1	1	100.00
		chip_sw_otbn_smoketest	12.018m	7.151ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.072m	6.383ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.854m	5.281ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.065m	2.879ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.801m	3.261ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.492m	3.486ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.899m	2.412ms	1	1	100.00
		chip_sw_uart_smoketest	2.950m	2.692ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.932m	2.849ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.360m	5.222ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.986h	59.727ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.612m	14.929ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.432m	5.733ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.334m	3.642ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.702m	3.366ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.789h	52.861ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.814h	56.260ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.632m	3.430ms	1	1	100.00
V2	tl_d_illegal_access	chip_tl_errors	2.632m	3.430ms	1	1	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.088h	38.706ms	1	1	100.00
		chip_same_csr_outstanding	19.822m	16.530ms	1	1	100.00
		chip_csr_hw_reset	4.170m	6.126ms	1	1	100.00
		chip_csr_rw	4.819m	5.468ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.088h	38.706ms	1	1	100.00
		chip_same_csr_outstanding	19.822m	16.530ms	1	1	100.00
		chip_csr_hw_reset	4.170m	6.126ms	1	1	100.00
		chip_csr_rw	4.819m	5.468ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	12.590s	123.469us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.070s	49.940us	1	1	100.00
		xbar_smoke_large_delays	1.071m	10.673ms	1	1	100.00
		xbar_smoke_slow_rsp	45.180s	5.154ms	1	1	100.00
		xbar_random_zero_delays	7.800s	62.462us	1	1	100.00
		xbar_random_large_delays	57.770s	9.510ms	1	1	100.00
		xbar_random_slow_rsp	4.565m	33.309ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	6.790s	49.684us	1	1	100.00
		xbar_error_and_unmapped_addr	18.980s	302.736us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	33.280s	1.669ms	1	1	100.00
		xbar_error_and_unmapped_addr	18.980s	302.736us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	37.660s	894.409us	1	1	100.00
		xbar_access_same_device_slow_rsp	4.538m	32.353ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	41.850s	1.862ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	4.173m	12.515ms	1	1	100.00
		xbar_stress_all_with_error	1.100m	3.451ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.602m	5.863ms	1	1	100.00
		xbar_stress_all_with_reset_error	5.590m	5.613ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.612m	14.929ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	34.364m	29.224ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.021m	16.005ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.676m	11.204ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	40.080m	15.312ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	38.477m	15.752ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.193m	16.294ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	37.117m	14.692ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.160s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.070s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.750s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.090s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.420s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.910s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.200s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.570s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.620s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.950s	10.100us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.490s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	15.520s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	20.620s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.730s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.050s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.720s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.770s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	16.840s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	15.770s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	16.020s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.720s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.920s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.510s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.640s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.840s	10.280us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.911m	11.139ms	1	1	100.00
		rom_e2e_asm_init_dev	36.292m	15.186ms	1	1	100.00
		rom_e2e_asm_init_prod	37.881m	16.038ms	1	1	100.00
		rom_e2e_asm_init_prod_end	38.323m	14.883ms	1	1	100.00
		rom_e2e_asm_init_rma	37.342m	14.872ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.424m	14.759ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.181m	14.863ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.345m	14.838ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	36.554m	15.607ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.824m	34.653ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.824m	34.653ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.374m	2.712ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.825m	3.416ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.145m	2.919ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.428m	3.127ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.967m	6.706ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.659m	3.298ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.347m	4.216ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.722m	5.042ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.174m	5.516ms	1	1	100.00
		chip_plic_all_irqs_10	4.325m	3.619ms	1	1	100.00
		chip_plic_all_irqs_20	5.313m	4.953ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.601m	3.296ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.538m	14.248ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.752m	4.283ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.290m	2.590ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	9.602m	10.100ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	15.568m	8.321ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	13.433m	6.953ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.421m	7.874ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.187h	255.065ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.592m	3.847ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	5.072m	6.383ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.592m	3.847ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.234m	7.174ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.234m	7.174ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.160m	6.671ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.075m	6.368ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	8.704m	5.879ms	1	1	100.00
		chip_sw_aes_idle	2.428m	3.127ms	1	1	100.00
		chip_sw_hmac_enc_idle	1.965m	2.769ms	1	1	100.00
		chip_sw_kmac_idle	1.905m	2.184ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.446m	4.642ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.551m	3.817ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.181m	4.876ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.971m	5.199ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.229m	8.556ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.490m	4.263ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.809m	4.915ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.285m	3.909ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.644m	4.905ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.539m	3.843ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.587m	4.102ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.761m	7.230ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.809m	5.240ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.285m	3.909ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.644m	4.905ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.505m	3.940ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.309m	6.165ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.423m	18.376ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.825m	3.416ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.591m	5.854ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.600m	2.385ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.846m	13.918ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.962m	2.445ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.508m	4.770ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.106m	3.230ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.896m	2.892ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.144m	4.436ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.421m	6.921ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	47.059m	23.988ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.533m	2.988ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.242m	2.955ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	10.272m	8.265ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.469m	3.152ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.033m	4.616ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.425m	22.215ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	25.911m	15.100ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.761m	7.230ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.752m	4.696ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.740m	3.290ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.722m	5.042ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	15.568m	8.321ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.206m	7.808ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.752m	4.393ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.887m	6.583ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.811m	2.899ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	23.302m	9.716ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.669m	2.209ms	1	1	100.00
		chip_sw_edn_entropy_reqs	11.037m	6.103ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.669m	2.209ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.206m	7.808ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.489m	3.346ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	16.348m	15.367ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.271m	5.750ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	8.309m	6.165ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.237m	3.974ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.505m	3.940ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	57.952m	45.179ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	16.348m	15.367ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.669m	2.540ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	12.531m	6.581ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.986m	4.810ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	57.952m	45.179ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.986m	4.810ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.986m	4.810ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.986m	4.810ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.986m	4.810ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.722m	5.042ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.264m	3.479ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	7.618m	4.515ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.284m	4.248ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.284m	4.248ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.506m	2.706ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.600m	2.385ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	1.965m	2.769ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.915m	2.533ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	6.247m	3.707ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.344m	5.840ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	4.798m	3.920ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.601m	4.829ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.716m	3.572ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	12.531m	6.581ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	23.846m	13.918ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	22.756m	10.999ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.967m	6.706ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	41.563m	16.106ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.786m	2.538ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.616m	2.921ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.962m	2.445ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	12.531m	6.581ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	9.556m	11.848ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.407m	2.834ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	18.886m	8.822ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.905m	2.184ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.347m	4.216ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	3.561m	4.197ms	1	1	100.00
		chip_tap_straps_rma	1.176m	2.673ms	1	1	100.00
		chip_tap_straps_prod	1.531m	2.779ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.439m	2.893ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	9.556m	11.848ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	9.556m	11.848ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	9.556m	11.848ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	17.573m	10.370ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.986m	4.810ms	1	1	100.00
		chip_sw_flash_rma_unlocked	57.952m	45.179ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.721m	3.243ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.670m	4.912ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.401m	7.933ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.347m	6.182ms	1	1	100.00
		chip_sw_lc_ctrl_transition	9.556m	11.848ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.531m	6.581ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.545m	8.474ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.150m	8.649ms	1	1	100.00
		chip_prim_tl_access	1.264m	3.479ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.809m	5.240ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.490m	4.263ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.809m	4.915ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.285m	3.909ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.644m	4.905ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.539m	3.843ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.587m	4.102ms	1	1	100.00
		chip_tap_straps_dev	3.561m	4.197ms	1	1	100.00
		chip_tap_straps_rma	1.176m	2.673ms	1	1	100.00
		chip_tap_straps_prod	1.531m	2.779ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.973m	10.900ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.830m	3.093ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.487m	3.719ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.203m	2.990ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.113m	3.281ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	23.973m	35.105ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.973m	10.900ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.080h	48.341ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	57.599m	51.256ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	7.317m	10.570ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.057h	48.247ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	23.973m	35.105ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	57.150s	2.490ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	58.800s	2.416ms	1	1	100.00
		rom_volatile_raw_unlock	58.870s	2.976ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	51.156m	16.732ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.423m	18.376ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	8.704m	5.879ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	8.704m	5.879ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	8.704m	5.879ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.463m	3.618ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	9.556m	11.848ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	16.348m	15.367ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.463m	3.618ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.531m	6.581ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.947m	5.097ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.664m	2.854ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	16.348m	15.367ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.463m	3.618ms	1	1	100.00
		chip_sw_keymgr_key_derivation	12.531m	6.581ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.947m	5.097ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.664m	2.854ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	9.556m	11.848ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.678m	5.180ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.439m	2.893ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.721m	3.243ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.670m	4.912ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.401m	7.933ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.347m	6.182ms	1	1	100.00
		chip_sw_lc_ctrl_transition	9.556m	11.848ms	1	1	100.00
		chip_prim_tl_access	1.264m	3.479ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.264m	3.479ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.482m	8.567ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.714m	8.849ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	16.928m	28.724ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.942m	8.162ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	8.631m	9.122ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.120m	6.325ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.205m	22.192ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	10.459m	13.751ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.234m	7.174ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.008m	9.058ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.280m	4.101ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.714m	8.849ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.941m	4.625ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	30.993m	35.384ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.847m	6.174ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.647m	4.904ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.313m	22.739ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.328m	7.074ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	10.247m	11.711ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	23.843m	21.060ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.953m	3.204ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.722m	5.042ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.545m	8.474ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.545m	8.474ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	10.247m	11.711ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	18.313m	22.739ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.280m	4.101ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	5.072m	6.383ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.769m	4.048ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.379m	5.164ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.008m	4.016ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.538m	14.248ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.367m	2.319ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.722m	5.042ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	13.433m	6.953ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.311m	4.450ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.191m	4.464ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.974m	3.269ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.664m	2.854ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.379m	5.164ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.379m	5.164ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	11.973m	9.959ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.596m	13.211ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.769m	4.048ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.970m	5.137ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.414m	5.426ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.176m	2.673ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.973m	10.900ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.174m	5.516ms	1	1	100.00
		chip_plic_all_irqs_10	4.325m	3.619ms	1	1	100.00
		chip_plic_all_irqs_20	5.313m	4.953ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.873m	2.350ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.846m	2.804ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.612m	14.929ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	5.631m	5.615ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.709m	2.811ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.395m	3.608ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.162m	3.614ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.947m	5.097ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.508m	4.770ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.353m	7.426ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.981m	7.532ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.150m	8.649ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.722m	5.042ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.850m	5.387ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	8.328m	7.074ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.692m	24.906ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.698m	2.735ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.006m	3.227ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.685m	4.059ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.692m	24.906ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.692m	24.906ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	12.249m	11.146ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	12.249m	11.146ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.441m	6.488ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.824m	34.653ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.072m	2.575ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.632m	2.454ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.088m	4.182ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.792m	3.844ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.077m	7.735ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.293h	31.489ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	27.642m	11.511ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.961m	2.919ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.358m	2.798ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.433m	3.001ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.428h	72.627ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.992m	5.838ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.434m	11.770ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.183m	11.364ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.789m	11.683ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.953m	4.606ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.359m	4.896ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.827m	3.927ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.845s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.641m	5.041ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.302m	2.829ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	9.511m	4.284ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	9.095m	5.726ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.436m	2.681ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.726m	4.884ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	58.900s	1.843ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	4.992m	5.236ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.046m	5.474ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.311m	3.694ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	10.247m	11.711ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.434m	11.770ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.183m	11.364ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.789m	11.683ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.300m	5.062ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.722m	5.042ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.340h	38.399ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.340h	38.399ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.909m	3.724ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.321m	4.650ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	47.820m	18.717ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.720m	2.414ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.999m	5.803ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.531m	3.067ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.769m	2.557ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.183m	3.174ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	15.081s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.492m	2.562ms	1	1	100.00
		TOTAL			286	325	88.00

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.28035198313291086222975258594125546302132598875882594257706160246751920628324
    Line 623, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.20046809054622761909888524515477880235181355454547555133556820903674449733528
    Line 721, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.92997599620867937712766726928199972639305127773523390677496635067794087316679
    Line 713, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.75695680594284473881896612699736511461964481703715398329353238814828451649604
    Line 699, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2826861490843432971207318311797344863236800622448370898358410217728764879805
    Line 814, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.71037282452695743621653797861287804016874510510835562574800589010194585103407
    Line 642, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.28496286611517721708697933072240289677330433977029292687299607754710121175804
    Line 604, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.8474798225139040015104324406242830766846014765214881574354386576091876716340
    Line 650, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.25134559569119116173836185178513408543302742890257851928287029784775825186548
    Line 618, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.51613730486236625559558169962042838455763984498790881058434494689420663096156
    Line 613, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.24268342196430418982372000071585287083155560103007856700817177614504813670543
    Line 700, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.22183521855640805172677479911416542196684608149366062535314306222952937616460
    Line 710, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.91994403566800784968768581861091504595720701820090010562478396848854811282732
    Line 655, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.25744413592126761675605918025971210102118532441892891947315956392535028021309
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 4.580s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.12919311755185370495037769526189062984949628038185804727348128900793850039746
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 2.095s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.92627831701979663883735372851065870624984626943219830830745691290002490335015
    Line 783, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.79216077417157836187013056249277454848390311051269193925200390161838253242663
    Line 591, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.30876617844301080093886859068295963866131775554093573356122704666997657323084
    Line 847, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.35075127495173908434591468953115122718115623458088892388894316133896714866257
    Line 688, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 1 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 1 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.7125542326927400900288669019052081375782111172562887407372300195082772971812
    Line 625, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 2865.780000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 2865.780000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.25614837375591771175078984999067682526014993932587359586943947452289344677866
    Line 422, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2810.877902 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2810.877902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@104059) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.78447136356559152177870486252985188516938434643207473589562682122872697895622
Line 441, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 5163.911000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@104059) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5163.911000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.62387522743064912063769983350422128495996384641178025138487374533418853994031
    Line 433, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11146.115792 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11146.115792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.91990441571828755505752131843807837898684797947516473772699937532384016414942
    Line 427, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34653.272415 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34653.272415 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.1784368787476122713839615786230424687837579390318464495143893602365375508343
    Line 406, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3298.181928 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 3298.181928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.34708973418515556436968612020216596875070770914767664523857920418342006917904
    Line 419, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2590.154332 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2590.154332 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.31102866498889755404593393391198944006665126478267500057295904121119328649846
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 3000.604696 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 3000.604696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.43733656625311848834173721487458137253085902308810528693392768855657002545171
    Line 421, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3641.610000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3641.610000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.32611573838629164860130111106314769688879100589518142069738712064247407356569
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3365.979500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3365.979500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.25006028424191089911484814664591333117486647223463738362044626872920726285906
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 12857.124209 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 12857.124209 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.115030382475701157253660674002624302064772347568490869752760089849320953872349
    Line 621, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.39041029406363524638607722659986671019728978838176281887905835357818749565877
    Line 748, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36115) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.54087227967862057274811243932162211337677071520297423529028721191737078680267
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2884.695890 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36115) { a_addr: 'h10a8  a_data: 'h98ce1452  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he  a_opcode: 'h0  a_user: 'h27ce6  d_param: 'h0  d_source: 'he  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2884.695890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---