ADC_CTRL Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	4.440s	5.774ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.910s	774.346us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.230s	338.736us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	18.970s	25.274ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.630s	730.948us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.270s	485.114us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.230s	338.736us	1	1	100.00
		adc_ctrl_csr_aliasing	3.630s	730.948us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.526m	491.856ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.517m	495.960ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	2.962m	163.716ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	6.649m	501.797ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	3.292m	371.056ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.597m	199.260ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.339m	175.153ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	3.575m	162.334ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	11.830s	4.908ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	13.870s	30.577ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	2.112m	79.234ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	4.301m	275.232ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.660s	405.703us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.780s	406.735us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.980s	443.718us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.980s	443.718us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.910s	774.346us	1	1	100.00
		adc_ctrl_csr_rw	2.230s	338.736us	1	1	100.00
		adc_ctrl_csr_aliasing	3.630s	730.948us	1	1	100.00
		adc_ctrl_same_csr_outstanding	9.810s	2.427ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.910s	774.346us	1	1	100.00
		adc_ctrl_csr_rw	2.230s	338.736us	1	1	100.00
		adc_ctrl_csr_aliasing	3.630s	730.948us	1	1	100.00
		adc_ctrl_same_csr_outstanding	9.810s	2.427ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	4.940s	7.669ms	1	1	100.00
		adc_ctrl_tl_intg_err	15.390s	8.684ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	15.390s	8.684ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	10.090s	7.225ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00