EDN Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.830s	35.148us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.680s	26.474us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.650s	201.529us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.180s	146.127us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.780s	119.261us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.130s	81.641us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.650s	201.529us	1	1	100.00
		edn_csr_aliasing	1.780s	119.261us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.080s	52.231us	1	1	100.00
V2	csrng_commands	edn_genbits	2.080s	52.231us	1	1	100.00
V2	genbits	edn_genbits	2.080s	52.231us	1	1	100.00
V2	interrupts	edn_intr	1.790s	23.642us	1	1	100.00
V2	alerts	edn_alert	2.060s	80.584us	1	1	100.00
V2	errs	edn_err	1.920s	36.235us	1	1	100.00
V2	disable	edn_disable	1.720s	11.696us	1	1	100.00
		edn_disable_auto_req_mode	1.920s	91.081us	1	1	100.00
V2	stress_all	edn_stress_all	5.950s	761.007us	1	1	100.00
V2	intr_test	edn_intr_test	1.800s	13.053us	1	1	100.00
V2	alert_test	edn_alert_test	1.890s	99.755us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.230s	244.184us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.230s	244.184us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.680s	26.474us	1	1	100.00
		edn_csr_rw	1.650s	201.529us	1	1	100.00
		edn_csr_aliasing	1.780s	119.261us	1	1	100.00
		edn_same_csr_outstanding	1.910s	21.364us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.680s	26.474us	1	1	100.00
		edn_csr_rw	1.650s	201.529us	1	1	100.00
		edn_csr_aliasing	1.780s	119.261us	1	1	100.00
		edn_same_csr_outstanding	1.910s	21.364us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.380s	1.010ms	1	1	100.00
		edn_tl_intg_err	2.770s	175.987us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.630s	42.489us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.060s	80.584us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.380s	1.010ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.380s	1.010ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.380s	1.010ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.380s	1.010ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.060s	80.584us	1	1	100.00
		edn_sec_cm	4.380s	1.010ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.060s	80.584us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.770s	175.987us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	23.670s	2.816ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00