c0fece9| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | entropy_src_smoke | 5.000s | 66.299us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | entropy_src_csr_hw_reset | 4.000s | 38.704us | 1 | 1 | 100.00 |
| V1 | csr_rw | entropy_src_csr_rw | 4.000s | 18.553us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | entropy_src_csr_bit_bash | 9.000s | 158.152us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | entropy_src_csr_aliasing | 5.000s | 135.100us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 5.000s | 68.524us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 4.000s | 18.553us | 1 | 1 | 100.00 |
| entropy_src_csr_aliasing | 5.000s | 135.100us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | firmware | entropy_src_smoke | 5.000s | 66.299us | 1 | 1 | 100.00 |
| entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 | ||
| entropy_src_fw_ov | 1.533m | 16.317ms | 1 | 1 | 100.00 | ||
| V2 | firmware_mode | entropy_src_fw_ov | 1.533m | 16.317ms | 1 | 1 | 100.00 |
| V2 | rng_mode | entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 |
| V2 | rng_max_rate | entropy_src_rng_max_rate | 13.000s | 257.356us | 0 | 1 | 0.00 |
| V2 | health_checks | entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 |
| V2 | conditioning | entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 |
| V2 | interrupts | entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 |
| entropy_src_intr | 9.000s | 290.580us | 1 | 1 | 100.00 | ||
| V2 | alerts | entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 |
| entropy_src_functional_alerts | 6.000s | 164.219us | 1 | 1 | 100.00 | ||
| V2 | stress_all | entropy_src_stress_all | 4.900m | 18.077ms | 1 | 1 | 100.00 |
| V2 | functional_errors | entropy_src_functional_errors | 5.000s | 83.446us | 1 | 1 | 100.00 |
| V2 | firmware_ov_read_contiguous_data | entropy_src_fw_ov_contiguous | 19.000s | 1.490ms | 1 | 1 | 100.00 |
| V2 | intr_test | entropy_src_intr_test | 4.000s | 32.709us | 1 | 1 | 100.00 |
| V2 | alert_test | entropy_src_alert_test | 4.000s | 64.863us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 5.000s | 113.335us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | entropy_src_tl_errors | 5.000s | 113.335us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 4.000s | 38.704us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 4.000s | 18.553us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 5.000s | 135.100us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 5.000s | 174.527us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 4.000s | 38.704us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 4.000s | 18.553us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 5.000s | 135.100us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 5.000s | 174.527us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 10 | 12 | 83.33 | |||
| V2S | tl_intg_err | entropy_src_sec_cm | 5.000s | 436.275us | 1 | 1 | 100.00 |
| entropy_src_tl_intg_err | 5.000s | 407.490us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_regwen | entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 |
| entropy_src_cfg_regwen | 4.000s | 150.727us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_mubi | entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 |
| V2S | sec_cm_config_redun | entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 |
| V2S | sec_cm_intersig_mubi | entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 |
| entropy_src_fw_ov | 1.533m | 16.317ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 83.446us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 436.275us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 83.446us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 436.275us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 4.000s | 14.325us | 0 | 1 | 0.00 |
| V2S | sec_cm_fifo_ctr_redun | entropy_src_functional_errors | 5.000s | 83.446us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 436.275us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 5.000s | 83.446us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 436.275us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 5.000s | 83.446us | 1 | 1 | 100.00 |
| V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 6.000s | 164.219us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 5.000s | 407.490us | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 4.000s | 15.595us | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 19 | 22 | 86.36 |
UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts has 2 failures:
Test entropy_src_rng_max_rate has 1 failures.
0.entropy_src_rng_max_rate.68189580643870798497535909383425337082160060676854685760201533258929821320331
Line 359, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_max_rate/latest/run.log
UVM_ERROR @ 257356389 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 257356389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test entropy_src_rng_with_xht_rsps has 1 failures.
0.entropy_src_rng_with_xht_rsps.32335804335395116079744664906468034283480341926643764678678057233366130431053
Line 155, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_with_xht_rsps/latest/run.log
UVM_ERROR @ 15594719 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 15594719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/fusesoc-work/src/lowrisc_fpv_entropy_src_csr_assert_*/entropy_src_csr_assert_fpv.sv,306): Assertion conf_rd_A has failed has 1 failures:
0.entropy_src_rng.63748428666066724489217481079465201409699956606755187648833319767506324551965
Line 155, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/fusesoc-work/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,306): (time 14324662 PS) Assertion tb.dut.entropy_src_csr_assert.conf_rd_A has failed
UVM_ERROR @ 14324662 ps: (entropy_src_csr_assert_fpv.sv:306) [ASSERT FAILED] conf_rd_A
UVM_INFO @ 14324662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---