HMAC Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 11.940s 6.096ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.650s 135.223us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.820s 24.671us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.580s 2.146ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.180s 200.115us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.120s 58.135us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.820s 24.671us 1 1 100.00
hmac_csr_aliasing 3.180s 200.115us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 18.520s 1.431ms 1 1 100.00
V2 back_pressure hmac_back_pressure 9.310s 1.055ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.640s 688.396us 1 1 100.00
hmac_test_sha384_vectors 19.310s 275.913us 1 1 100.00
hmac_test_sha512_vectors 18.800s 236.875us 1 1 100.00
hmac_test_hmac256_vectors 8.370s 258.313us 1 1 100.00
hmac_test_hmac384_vectors 8.050s 551.942us 1 1 100.00
hmac_test_hmac512_vectors 9.320s 542.343us 1 1 100.00
V2 burst_wr hmac_burst_wr 14.990s 3.124ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 8.201m 11.275ms 1 1 100.00
V2 error hmac_error 12.380s 3.770ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 42.750s 5.094ms 1 1 100.00
V2 save_and_restore hmac_smoke 11.940s 6.096ms 1 1 100.00
hmac_long_msg 18.520s 1.431ms 1 1 100.00
hmac_back_pressure 9.310s 1.055ms 1 1 100.00
hmac_datapath_stress 8.201m 11.275ms 1 1 100.00
hmac_burst_wr 14.990s 3.124ms 1 1 100.00
hmac_stress_all 10.412m 162.674ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 11.940s 6.096ms 1 1 100.00
hmac_long_msg 18.520s 1.431ms 1 1 100.00
hmac_back_pressure 9.310s 1.055ms 1 1 100.00
hmac_datapath_stress 8.201m 11.275ms 1 1 100.00
hmac_wipe_secret 42.750s 5.094ms 1 1 100.00
hmac_test_sha256_vectors 8.640s 688.396us 1 1 100.00
hmac_test_sha384_vectors 19.310s 275.913us 1 1 100.00
hmac_test_sha512_vectors 18.800s 236.875us 1 1 100.00
hmac_test_hmac256_vectors 8.370s 258.313us 1 1 100.00
hmac_test_hmac384_vectors 8.050s 551.942us 1 1 100.00
hmac_test_hmac512_vectors 9.320s 542.343us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 11.940s 6.096ms 1 1 100.00
hmac_long_msg 18.520s 1.431ms 1 1 100.00
hmac_back_pressure 9.310s 1.055ms 1 1 100.00
hmac_datapath_stress 8.201m 11.275ms 1 1 100.00
hmac_burst_wr 14.990s 3.124ms 1 1 100.00
hmac_error 12.380s 3.770ms 1 1 100.00
hmac_wipe_secret 42.750s 5.094ms 1 1 100.00
hmac_test_sha256_vectors 8.640s 688.396us 1 1 100.00
hmac_test_sha384_vectors 19.310s 275.913us 1 1 100.00
hmac_test_sha512_vectors 18.800s 236.875us 1 1 100.00
hmac_test_hmac256_vectors 8.370s 258.313us 1 1 100.00
hmac_test_hmac384_vectors 8.050s 551.942us 1 1 100.00
hmac_test_hmac512_vectors 9.320s 542.343us 1 1 100.00
hmac_stress_all 10.412m 162.674ms 1 1 100.00
V2 stress_all hmac_stress_all 10.412m 162.674ms 1 1 100.00
V2 alert_test hmac_alert_test 1.390s 13.667us 1 1 100.00
V2 intr_test hmac_intr_test 1.460s 22.718us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.440s 107.830us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.440s 107.830us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.650s 135.223us 1 1 100.00
hmac_csr_rw 1.820s 24.671us 1 1 100.00
hmac_csr_aliasing 3.180s 200.115us 1 1 100.00
hmac_same_csr_outstanding 2.740s 46.779us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.650s 135.223us 1 1 100.00
hmac_csr_rw 1.820s 24.671us 1 1 100.00
hmac_csr_aliasing 3.180s 200.115us 1 1 100.00
hmac_same_csr_outstanding 2.740s 46.779us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.850s 245.281us 1 1 100.00
hmac_tl_intg_err 4.160s 238.016us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.160s 238.016us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 11.940s 6.096ms 1 1 100.00
V3 stress_reset hmac_stress_reset 6.780s 137.111us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.215m 20.974ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.890s 42.409us 1 1 100.00
TOTAL 28 28 100.00