I2C Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: `c0fece9`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	38.390s	16.586ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	33.110s	13.053ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.560s	38.629us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.640s	21.957us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.380s	250.015us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.250s	65.128us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.860s	94.358us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.640s	21.957us	1	1	100.00
		i2c_csr_aliasing	2.250s	65.128us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.180s	173.001us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	14.350m	353.089ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.707m	18.375ms	1	1	100.00
V2	host_override	i2c_host_override	1.660s	20.938us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.431m	9.265ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	35.390s	6.942ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.940s	116.962us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.210s	1.500ms	1	1	100.00
		i2c_host_fifo_reset_rx	8.570s	727.731us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.509m	2.434ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	27.170s	1.741ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.220s	70.587us	0	1	0.00
V2	target_glitch	i2c_target_glitch	9.470s	2.067ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.259m	46.138ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.780s	3.214ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	16.530s	1.404ms	1	1	100.00
		i2c_target_intr_smoke	9.590s	5.833ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.020s	488.257us	1	1	100.00
		i2c_target_fifo_reset_tx	1.950s	720.549us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	4.273m	54.027ms	1	1	100.00
		i2c_target_stress_rd	16.530s	1.404ms	1	1	100.00
		i2c_target_intr_stress_wr	42.960s	25.369ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	7.020s	1.059ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	8.480s	2.146ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.950s	1.287ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	12.830s	10.088ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.390s	1.216ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.760s	515.377us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.707m	18.375ms	1	1	100.00
		i2c_host_perf_precise	2.080s	101.274us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	27.170s	1.741ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	1.780s	38.775us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.090s	1.730ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.740s	1.680ms	1	1	100.00
		i2c_target_nack_txstretch	2.290s	558.914us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	13.520s	434.614us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.740s	996.569us	1	1	100.00
V2	alert_test	i2c_alert_test	1.560s	61.669us	1	1	100.00
V2	intr_test	i2c_intr_test	1.610s	22.230us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.410s	53.549us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.410s	53.549us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.560s	38.629us	1	1	100.00
		i2c_csr_rw	1.640s	21.957us	1	1	100.00
		i2c_csr_aliasing	2.250s	65.128us	1	1	100.00
		i2c_same_csr_outstanding	2.340s	183.613us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.560s	38.629us	1	1	100.00
		i2c_csr_rw	1.640s	21.957us	1	1	100.00
		i2c_csr_aliasing	2.250s	65.128us	1	1	100.00
		i2c_same_csr_outstanding	2.340s	183.613us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	3.110s	281.934us	1	1	100.00
		i2c_sec_cm	1.600s	145.512us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.110s	281.934us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	18.310s	947.535us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.810s	2.196ms	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	6.290s	910.546us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.81231375933122538082949139704033377744403362647895530175195657454470933065115
Line 156, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 353089020115 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @11097420

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.87639456727320490998430222066504844083059716886998954108278940935610912251533
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  70586790 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @30297

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.109320892485668835982728081862303364691900926715034765960732331041096440175727
    Line 98, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 947535293 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 947535293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.62299489822627525058646791514622255274379954444149388830068649483956600063751
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 910545975 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 910545975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.38949297079124232847467764855314771957576055045844152996954807440786316469122
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 2195517027 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2195517027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.62383252697065405953681834172877772004378544811703271606023318656431639839500
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10088463796 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10088463796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```