KEYMGR Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.880s	211.295us	1	1	100.00
V1	random	keymgr_random	41.170s	3.952ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.950s	63.424us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.010s	64.464us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	8.520s	251.571us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.470s	589.577us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.300s	172.143us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.010s	64.464us	1	1	100.00
		keymgr_csr_aliasing	6.470s	589.577us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	5.950s	530.956us	1	1	100.00
V2	sideload	keymgr_sideload	3.620s	132.410us	1	1	100.00
		keymgr_sideload_kmac	2.540s	99.424us	1	1	100.00
		keymgr_sideload_aes	3.040s	61.466us	1	1	100.00
		keymgr_sideload_otbn	3.610s	2.045ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.250s	68.430us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.120s	27.138us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.840s	249.737us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	6.350s	227.737us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.550s	98.284us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.890s	304.529us	1	1	100.00
V2	stress_all	keymgr_stress_all	10.580s	1.171ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.580s	20.785us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.700s	43.877us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.230s	1.392ms	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.230s	1.392ms	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.950s	63.424us	1	1	100.00
		keymgr_csr_rw	2.010s	64.464us	1	1	100.00
		keymgr_csr_aliasing	6.470s	589.577us	1	1	100.00
		keymgr_same_csr_outstanding	2.010s	81.234us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.950s	63.424us	1	1	100.00
		keymgr_csr_rw	2.010s	64.464us	1	1	100.00
		keymgr_csr_aliasing	6.470s	589.577us	1	1	100.00
		keymgr_same_csr_outstanding	2.010s	81.234us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
		keymgr_tl_intg_err	7.150s	504.289us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.670s	70.014us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.670s	70.014us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.670s	70.014us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.670s	70.014us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.470s	1.709ms	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.150s	504.289us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.670s	70.014us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	5.950s	530.956us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	41.170s	3.952ms	1	1	100.00
		keymgr_csr_rw	2.010s	64.464us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	41.170s	3.952ms	1	1	100.00
		keymgr_csr_rw	2.010s	64.464us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	41.170s	3.952ms	1	1	100.00
		keymgr_csr_rw	2.010s	64.464us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.120s	27.138us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.550s	98.284us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.550s	98.284us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	41.170s	3.952ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.810s	40.490us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.380s	143.227us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.120s	27.138us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.380s	143.227us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.380s	143.227us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.380s	143.227us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.570s	921.867us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.380s	143.227us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	3.160s	479.701us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.35962578942313488696561812784866305359900707758964854253186603896571507839020
      Line 222, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 479700944 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 479700944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---