KMAC/MASKED Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	7.520s	1.442ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.730s	29.981us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.920s	76.399us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.100s	6.010ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.090s	974.351us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.790s	255.697us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.920s	76.399us	1	1	100.00
		kmac_csr_aliasing	5.090s	974.351us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.650s	41.933us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.990s	19.218us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	6.494m	96.045ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.864m	48.508ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.590s	7.084ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.671m	182.596ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.680s	3.685ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.927m	126.875ms	1	1	100.00
		kmac_test_vectors_shake_128	2.869m	33.758ms	1	1	100.00
		kmac_test_vectors_shake_256	4.805m	11.248ms	1	1	100.00
		kmac_test_vectors_kmac	3.340s	89.882us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.980s	178.419us	1	1	100.00
V2	sideload	kmac_sideload	2.271m	36.469ms	1	1	100.00
V2	app	kmac_app	11.000s	598.235us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.863m	68.964ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.275m	185.907ms	1	1	100.00
V2	error	kmac_error	3.130m	15.643ms	1	1	100.00
V2	key_error	kmac_key_error	5.050s	1.665ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.680s	101.306us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	27.760s	14.493ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.220s	157.942us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	33.860s	7.872ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.120s	38.886us	1	1	100.00
V2	stress_all	kmac_stress_all	16.779m	63.031ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.720s	13.448us	1	1	100.00
V2	alert_test	kmac_alert_test	1.660s	19.453us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.600s	470.238us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.600s	470.238us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.730s	29.981us	1	1	100.00
		kmac_csr_rw	1.920s	76.399us	1	1	100.00
		kmac_csr_aliasing	5.090s	974.351us	1	1	100.00
		kmac_same_csr_outstanding	2.150s	326.604us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.730s	29.981us	1	1	100.00
		kmac_csr_rw	1.920s	76.399us	1	1	100.00
		kmac_csr_aliasing	5.090s	974.351us	1	1	100.00
		kmac_same_csr_outstanding	2.150s	326.604us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.370s	160.997us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.370s	160.997us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.370s	160.997us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.370s	160.997us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.330s	362.567us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.159m	54.000ms	1	1	100.00
		kmac_tl_intg_err	1.850s	36.072us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.850s	36.072us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.120s	38.886us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	7.520s	1.442ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.271m	36.469ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.370s	160.997us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.159m	54.000ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.159m	54.000ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.159m	54.000ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	7.520s	1.442ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.120s	38.886us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.159m	54.000ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.190m	14.054ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	7.520s	1.442ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.932m	3.095ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.74574537495185379850040505940489300256788632408118944492297095063888197703265
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
        UVM_ERROR @  36071745 ps: (kmac_csr_assert_fpv.sv:560) [ASSERT FAILED] prefix_10_rd_A
        UVM_INFO @  36071745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---