KMAC/UNMASKED Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	6.120s	401.338us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.820s	107.691us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.680s	13.145us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.600s	1.971ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.740s	81.225us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.330s	50.997us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.680s	13.145us	1	1	100.00
		kmac_csr_aliasing	3.740s	81.225us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.570s	27.898us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.950s	249.778us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	4.176m	15.130ms	1	1	100.00
V2	burst_write	kmac_burst_write	42.430s	2.300ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.324m	400.535ms	1	1	100.00
		kmac_test_vectors_sha3_256	33.450s	2.369ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.060s	1.408ms	1	1	100.00
		kmac_test_vectors_sha3_512	8.972m	18.198ms	1	1	100.00
		kmac_test_vectors_shake_128	2.334m	40.924ms	1	1	100.00
		kmac_test_vectors_shake_256	3.301m	9.533ms	1	1	100.00
		kmac_test_vectors_kmac	2.720s	33.963us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.470s	264.381us	1	1	100.00
V2	sideload	kmac_sideload	4.574m	51.062ms	1	1	100.00
V2	app	kmac_app	3.002m	5.786ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.649m	26.348ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.227m	218.158ms	1	1	100.00
V2	error	kmac_error	4.008m	33.317ms	1	1	100.00
V2	key_error	kmac_key_error	5.310s	2.463ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.500s	154.554us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	15.350s	3.080ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	31.120s	1.469ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	42.510s	5.739ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.840s	62.412us	1	1	100.00
V2	stress_all	kmac_stress_all	1.690m	2.844ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.640s	44.338us	1	1	100.00
V2	alert_test	kmac_alert_test	1.670s	46.293us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.420s	36.379us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.420s	36.379us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.820s	107.691us	1	1	100.00
		kmac_csr_rw	1.680s	13.145us	1	1	100.00
		kmac_csr_aliasing	3.740s	81.225us	1	1	100.00
		kmac_same_csr_outstanding	2.730s	177.451us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.820s	107.691us	1	1	100.00
		kmac_csr_rw	1.680s	13.145us	1	1	100.00
		kmac_csr_aliasing	3.740s	81.225us	1	1	100.00
		kmac_same_csr_outstanding	2.730s	177.451us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.770s	23.496us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.770s	23.496us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.770s	23.496us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.770s	23.496us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.760s	70.100us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	46.820s	10.749ms	1	1	100.00
		kmac_tl_intg_err	1.840s	22.622us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.840s	22.622us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.840s	62.412us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	6.120s	401.338us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.574m	51.062ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.770s	23.496us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	46.820s	10.749ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	46.820s	10.749ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	46.820s	10.749ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	6.120s	401.338us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.840s	62.412us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	46.820s	10.749ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	35.130s	972.614us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	6.120s	401.338us	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.969m	10.801ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.101738822286984305472340858340672869519563362039525151583619976232755139736442
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @  70099637 ps: (kmac_csr_assert_fpv.sv:506) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @  70099637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.52315024074633339024176799500501791713139399684753103225851345533188616166339
      Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
        UVM_ERROR @  22622188 ps: (kmac_csr_assert_fpv.sv:554) [ASSERT FAILED] prefix_9_rd_A
        UVM_INFO @  22622188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.49802841086879247190723614936296581086205871825966887357581929266622304473981
      Line 243, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10800705900 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 10800705900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---