ROM_CTRL/32KB Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.210s 188.999us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.110s 307.678us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.950s 166.703us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.320s 1.036ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 3.690s 213.600us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.360s 222.809us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.950s 166.703us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 213.600us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.050s 169.073us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 3.680s 206.288us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.140s 310.625us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 9.520s 2.329ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.560s 714.056us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.130s 124.590us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.250s 173.760us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.250s 173.760us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.110s 307.678us 1 1 100.00
rom_ctrl_csr_rw 4.950s 166.703us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 213.600us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.480s 403.502us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.110s 307.678us 1 1 100.00
rom_ctrl_csr_rw 4.950s 166.703us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 213.600us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.480s 403.502us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 58.580s 2.298ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 11.890s 856.851us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.895m 902.282us 1 1 100.00
rom_ctrl_tl_intg_err 37.790s 2.813ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.895m 902.282us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.895m 902.282us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 58.580s 2.298ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 58.580s 2.298ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 58.580s 2.298ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 58.580s 2.298ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 58.580s 2.298ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.895m 902.282us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.895m 902.282us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.210s 188.999us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.210s 188.999us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.210s 188.999us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 37.790s 2.813ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 58.580s 2.298ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.560s 714.056us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 58.580s 2.298ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 58.580s 2.298ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 58.580s 2.298ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 11.890s 856.851us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.895m 902.282us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.532m 13.563ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00