ROM_CTRL/64KB Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.830s 3.972ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.840s 710.327us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.640s 730.237us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.580s 378.872us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.240s 1.138ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.230s 233.926us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.640s 730.237us 1 1 100.00
rom_ctrl_csr_aliasing 6.240s 1.138ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.570s 212.535us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.850s 212.395us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.100s 1.544ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 18.670s 584.434us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.330s 1.039ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.390s 755.500us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.670s 532.720us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.670s 532.720us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.840s 710.327us 1 1 100.00
rom_ctrl_csr_rw 5.640s 730.237us 1 1 100.00
rom_ctrl_csr_aliasing 6.240s 1.138ms 1 1 100.00
rom_ctrl_same_csr_outstanding 8.580s 604.840us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.840s 710.327us 1 1 100.00
rom_ctrl_csr_rw 5.640s 730.237us 1 1 100.00
rom_ctrl_csr_aliasing 6.240s 1.138ms 1 1 100.00
rom_ctrl_same_csr_outstanding 8.580s 604.840us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.371m 5.440ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 32.010s 6.055ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.426m 467.873us 1 1 100.00
rom_ctrl_tl_intg_err 34.770s 328.084us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.426m 467.873us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.426m 467.873us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.371m 5.440ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.371m 5.440ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.371m 5.440ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.371m 5.440ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.371m 5.440ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.426m 467.873us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.426m 467.873us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.830s 3.972ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.830s 3.972ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.830s 3.972ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 34.770s 328.084us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.371m 5.440ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.330s 1.039ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.371m 5.440ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.371m 5.440ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.371m 5.440ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 32.010s 6.055ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.426m 467.873us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.587m 8.578ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00