RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.190s 680.963us 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.170s 208.497us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 2.140s 882.263us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 8.200s 6.400ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.460s 827.734us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 21.150s 19.041ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 3.980s 8.457ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 25.450s 15.627ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.018m 31.691ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 2.450s 1.095ms 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.920s 126.870us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.770s 335.398us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.780s 180.680us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.760s 166.288us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.910s 282.893us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.820s 135.291us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 3.930s 1.258ms 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 2.450s 1.095ms 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.770s 509.902us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 1.730s 501.621us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.770s 335.398us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.700s 59.118us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.230s 85.746us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 3.800s 117.797us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 36.690s 1.544ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 18.070s 549.730us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.570s 75.966us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 18.070s 549.730us 1 1 100.00
rv_dm_csr_rw 3.800s 117.797us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 2.080s 81.621us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.890s 61.412us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 3.190s 680.963us 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.810s 171.569us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.000s 212.062us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 2.000s 300.725us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.980s 594.459us 1 1 100.00
V2 sba rv_dm_sba_tl_access 2.560s 4.559ms 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 1.920s 109.924us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 2.560s 2.819ms 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 17.450s 23.006ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 1.900s 166.020us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 1.890s 1.280ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.760s 345.236us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.870s 152.556us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 11.180s 10.756ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 1.660s 38.235us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.850s 112.819us 1 1 100.00
V2 stress_all rv_dm_stress_all 4.720s 1.905ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.630s 90.793us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 2.070s 58.389us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 2.070s 58.389us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 18.070s 549.730us 1 1 100.00
rv_dm_csr_hw_reset 2.230s 85.746us 1 1 100.00
rv_dm_csr_rw 3.800s 117.797us 1 1 100.00
rv_dm_same_csr_outstanding 5.970s 161.075us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 18.070s 549.730us 1 1 100.00
rv_dm_csr_hw_reset 2.230s 85.746us 1 1 100.00
rv_dm_csr_rw 3.800s 117.797us 1 1 100.00
rv_dm_same_csr_outstanding 5.970s 161.075us 1 1 100.00
V2 TOTAL 16 19 84.21
V2S tl_intg_err rv_dm_sec_cm 2.060s 204.145us 1 1 100.00
rv_dm_tl_intg_err 7.770s 1.993ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 7.770s 1.993ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 1.890s 1.280ms 1 1 100.00
rv_dm_debug_disabled 1.730s 155.161us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 1.890s 1.280ms 1 1 100.00
rv_dm_debug_disabled 1.730s 155.161us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 3.190s 680.963us 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.850s 337.816us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.810s 198.599us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.810s 198.599us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.850s 337.816us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 1.680s 132.150us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.610s 35.690us 1 1 100.00
TOTAL 48 53 90.57

Failure Buckets