| V1 |
random |
rv_timer_random |
1.570s |
50.835us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.400s |
35.613us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.460s |
18.453us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
3.470s |
599.869us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.560s |
59.643us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
1.660s |
21.991us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.460s |
18.453us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.560s |
59.643us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
1.620s |
1.937ms |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
1.930s |
3.283ms |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
1.490s |
144.338us |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
1.490s |
144.338us |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
1.490s |
46.222us |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.560s |
44.692us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.520s |
41.399us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
3.100s |
55.041us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
3.100s |
55.041us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.400s |
35.613us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.460s |
18.453us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.560s |
59.643us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.590s |
42.957us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.400s |
35.613us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.460s |
18.453us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.560s |
59.643us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.590s |
42.957us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.760s |
236.932us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
2.140s |
78.224us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
2.140s |
78.224us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.590s |
35.122us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.480s |
26.799us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
11.350s |
1.234ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |