SPI_DEVICE/1R1W Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	16.070s	6.973ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.990s	53.217us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.010s	68.969us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.900s	3.060ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	12.350s	231.005us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.110s	149.989us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.010s	68.969us	1	1	100.00
		spi_device_csr_aliasing	12.350s	231.005us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.570s	11.848us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.520s	23.680us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	2.080s	31.385us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.670s	1.769us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.760s	3.837us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.650s	35.906us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.650s	35.906us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.780s	6.154ms	1	1	100.00
		spi_device_tpm_sts_read	1.890s	54.449us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	16.600s	9.021ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.360s	4.216ms	1	1	100.00
		spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.060s	228.418us	1	1	100.00
		spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.060s	228.418us	1	1	100.00
		spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	13.730s	7.823ms	1	1	100.00
		spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	13.730s	7.823ms	1	1	100.00
		spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	13.730s	7.823ms	1	1	100.00
		spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	13.730s	7.823ms	1	1	100.00
		spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	13.730s	7.823ms	1	1	100.00
		spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.290s	691.537us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	11.440s	1.135ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	11.440s	1.135ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	11.440s	1.135ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	41.120s	3.489ms	1	1	100.00
		spi_device_read_buffer_direct	6.130s	2.732ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	11.440s	1.135ms	1	1	100.00
		spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	15.730s	7.828ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.250s	354.339us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.250s	354.339us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	16.070s	6.973ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	14.020s	1.784ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.359m	45.269ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.900s	64.264us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.810s	49.141us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.660s	80.049us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.660s	80.049us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.990s	53.217us	1	1	100.00
		spi_device_csr_rw	3.010s	68.969us	1	1	100.00
		spi_device_csr_aliasing	12.350s	231.005us	1	1	100.00
		spi_device_same_csr_outstanding	2.640s	28.727us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.990s	53.217us	1	1	100.00
		spi_device_csr_rw	3.010s	68.969us	1	1	100.00
		spi_device_csr_aliasing	12.350s	231.005us	1	1	100.00
		spi_device_same_csr_outstanding	2.640s	28.727us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.220s	582.071us	1	1	100.00
		spi_device_tl_intg_err	11.050s	2.716ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.050s	2.716ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	24.060s	1.528ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.52079185599021505211417438929174158395992398914779983947985277496764013855640
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1133843 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[48])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1133843 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1133843 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[944])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.74821912042053339792948588501333232892090751423459688422733586795763069148022
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1271249 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x17ce44 [101111100111001000100] vs 0x0 [0])
        UVM_ERROR @   1352249 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9ae246 [100110101110001001000110] vs 0x0 [0])
        UVM_ERROR @   1374249 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5d46b2 [10111010100011010110010] vs 0x0 [0])
        UVM_ERROR @   1439249 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x516178 [10100010110000101111000] vs 0x0 [0])
        UVM_ERROR @   1466249 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2e634c [1011100110001101001100] vs 0x0 [0])