SPI_DEVICE/2P Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.927m	73.514ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.780s	33.488us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.250s	84.997us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.330s	1.465ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.960s	5.297ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.440s	207.815us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.250s	84.997us	1	1	100.00
		spi_device_csr_aliasing	16.960s	5.297ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.690s	12.684us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.520s	86.250us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.740s	14.092us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.820s	15.512us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	1.570s	34.692us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	6.050s	562.601us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	6.050s	562.601us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.200s	1.301ms	1	1	100.00
		spi_device_tpm_sts_read	1.810s	82.630us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	7.690s	593.869us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.130s	121.098us	1	1	100.00
		spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.150s	318.167us	1	1	100.00
		spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.150s	318.167us	1	1	100.00
		spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	13.060s	2.993ms	1	1	100.00
		spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	13.060s	2.993ms	1	1	100.00
		spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	13.060s	2.993ms	1	1	100.00
		spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	13.060s	2.993ms	1	1	100.00
		spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	13.060s	2.993ms	1	1	100.00
		spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.410s	2.416ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	8.940s	618.684us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	8.940s	618.684us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	8.940s	618.684us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.940s	633.607us	1	1	100.00
		spi_device_read_buffer_direct	4.210s	554.515us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	8.940s	618.684us	1	1	100.00
		spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	26.530s	9.645ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.330s	2.303ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.330s	2.303ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.927m	73.514ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.382m	31.221ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.183m	6.549ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.750s	43.384us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.760s	13.605us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.250s	28.539us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.250s	28.539us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.780s	33.488us	1	1	100.00
		spi_device_csr_rw	2.250s	84.997us	1	1	100.00
		spi_device_csr_aliasing	16.960s	5.297ms	1	1	100.00
		spi_device_same_csr_outstanding	2.650s	159.192us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.780s	33.488us	1	1	100.00
		spi_device_csr_rw	2.250s	84.997us	1	1	100.00
		spi_device_csr_aliasing	16.960s	5.297ms	1	1	100.00
		spi_device_same_csr_outstanding	2.650s	159.192us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.790s	263.252us	1	1	100.00
		spi_device_tl_intg_err	5.670s	107.921us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.670s	107.921us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	50.820s	9.722ms	1	1	100.00
		TOTAL			33	33	100.00