SPI_HOST Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	21.000s	189.968us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	24.943us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	30.857us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	413.589us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	3.000s	30.408us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	45.104us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	30.857us	1	1	100.00
		spi_host_csr_aliasing	3.000s	30.408us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	16.143us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	65.642us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	49.501us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	173.088us	1	1	100.00
		spi_host_error_cmd	4.000s	23.440us	1	1	100.00
		spi_host_event	11.300m	70.356ms	1	1	100.00
V2	clock_rate	spi_host_speed	13.000s	246.653us	1	1	100.00
V2	speed	spi_host_speed	13.000s	246.653us	1	1	100.00
V2	chip_select_timing	spi_host_speed	13.000s	246.653us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.000s	39.511us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	60.099us	1	1	100.00
V2	cpol_cpha	spi_host_speed	13.000s	246.653us	1	1	100.00
V2	full_cycle	spi_host_speed	13.000s	246.653us	1	1	100.00
V2	duplex	spi_host_smoke	21.000s	189.968us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	21.000s	189.968us	1	1	100.00
V2	stress_all	spi_host_stress_all	27.000s	8.877ms	1	1	100.00
V2	spien	spi_host_spien	8.000s	1.198ms	1	1	100.00
V2	stall	spi_host_status_stall	20.000s	2.503ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	47.231us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	173.088us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	67.834us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	46.207us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	44.210us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	44.210us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	24.943us	1	1	100.00
		spi_host_csr_rw	4.000s	30.857us	1	1	100.00
		spi_host_csr_aliasing	3.000s	30.408us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	34.300us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	24.943us	1	1	100.00
		spi_host_csr_rw	4.000s	30.857us	1	1	100.00
		spi_host_csr_aliasing	3.000s	30.408us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	34.300us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	175.723us	1	1	100.00
		spi_host_sec_cm	4.000s	70.628us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	175.723us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	2.367m	200.000ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.54511479355129326629769104373949571453103241694884588735072488308169522882768
      Line 129, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---