SRAM_CTRL/MAIN Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	5.640s	1.523ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.590s	23.717us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.550s	41.928us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.240s	85.751us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.450s	18.165us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.040s	369.390us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.550s	41.928us	1	1	100.00
		sram_ctrl_csr_aliasing	1.450s	18.165us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.616m	5.531ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	59.020s	10.938ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.872m	49.368ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.978m	13.377ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	17.259m	68.045ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.965m	13.557ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.940s	2.045ms	1	1	100.00
V2	executable	sram_ctrl_executable	2.280m	28.051ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.390s	3.217ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.069m	15.829ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	40.440s	1.161ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	34.010s	3.343ms	1	1	100.00
		sram_ctrl_throughput_w_readback	10.290s	785.711us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.854m	13.946ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.930s	347.401us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	30.159m	248.759ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.530s	24.020us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.200s	263.593us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.200s	263.593us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.590s	23.717us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	41.928us	1	1	100.00
		sram_ctrl_csr_aliasing	1.450s	18.165us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.480s	33.265us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.590s	23.717us	1	1	100.00
		sram_ctrl_csr_rw	1.550s	41.928us	1	1	100.00
		sram_ctrl_csr_aliasing	1.450s	18.165us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.480s	33.265us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.580s	7.391ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.440s	3.496us	0	1	0.00
		sram_ctrl_tl_intg_err	2.830s	168.271us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.440s	3.496us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.830s	168.271us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.854m	13.946ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.854m	13.946ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.550s	41.928us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.280m	28.051ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.280m	28.051ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.280m	28.051ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.940s	2.045ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.790s	715.181us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.580s	7.391ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.170s	4.711ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	5.640s	1.523ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	5.640s	1.523ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.280m	28.051ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.440s	3.496us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.940s	2.045ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.440s	3.496us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.440s	3.496us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	5.640s	1.523ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.440s	3.496us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.360s	4.101ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.103449528114792999456858903974602747688891035957273588462334646168915917542339
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3496008 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3496008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---