SRAM_CTRL/RET Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	17.220s	840.481us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.470s	15.748us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.560s	22.013us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.310s	82.840us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.730s	66.972us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.940s	128.499us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.560s	22.013us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	66.972us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.720s	1.882ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.500s	732.462us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	29.590s	794.152us	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.274m	17.571ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	53.340s	18.985ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.139m	7.153ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.600s	510.765us	1	1	100.00
V2	executable	sram_ctrl_executable	10.182m	6.436ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.950s	1.273ms	1	1	100.00
		sram_ctrl_partial_access_b2b	2.830m	3.271ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	5.370s	106.806us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	42.590s	148.972us	1	1	100.00
		sram_ctrl_throughput_w_readback	56.340s	609.410us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.792m	60.337ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.580s	30.800us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	34.476m	27.167ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.870s	18.051us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.070s	562.200us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.070s	562.200us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.470s	15.748us	1	1	100.00
		sram_ctrl_csr_rw	1.560s	22.013us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	66.972us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	25.711us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.470s	15.748us	1	1	100.00
		sram_ctrl_csr_rw	1.560s	22.013us	1	1	100.00
		sram_ctrl_csr_aliasing	1.730s	66.972us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.650s	25.711us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.990s	404.779us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.620s	7.525us	0	1	0.00
		sram_ctrl_tl_intg_err	2.880s	680.879us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.620s	7.525us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.880s	680.879us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.792m	60.337ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.792m	60.337ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.560s	22.013us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.182m	6.436ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.182m	6.436ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.182m	6.436ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.600s	510.765us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.010s	147.627us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.990s	404.779us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.950s	165.598us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	17.220s	840.481us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	17.220s	840.481us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.182m	6.436ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.620s	7.525us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.600s	510.765us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.620s	7.525us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.620s	7.525us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	17.220s	840.481us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.620s	7.525us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	21.130s	1.948ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.35685637739534358317973158313305492353505607000388322664927113630974480782841
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7524758 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7524758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---