SYSRST_CTRL Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: `c0fece9`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	2.770s	2.125ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.510s	2.471ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.200s	2.404ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.630s	2.533ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	3.350s	4.075ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	3.130s	2.044ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.979m	40.157ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	7.550s	2.675ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	4.270s	2.108ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	3.130s	2.044ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.550s	2.675ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	3.531m	117.805ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	15.180s	59.663ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	6.960s	3.083ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	6.270s	4.246ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	2.960s	2.540ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	2.530s	2.173ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	4.230s	2.741ms	0	1	0.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	3.870s	2.617ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	1.940s	3.331ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.267m	37.280ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	6.130s	12.683ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	8.150s	2.016ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	5.920s	2.013ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.350s	2.602ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.350s	2.602ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	3.350s	4.075ms	1	1	100.00
		sysrst_ctrl_csr_rw	3.130s	2.044ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.550s	2.675ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	14.260s	4.759ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	3.350s	4.075ms	1	1	100.00
		sysrst_ctrl_csr_rw	3.130s	2.044ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.550s	2.675ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	14.260s	4.759ms	1	1	100.00
V2		TOTAL			13	15	86.67
V2S	tl_intg_err	sysrst_ctrl_sec_cm	54.250s	42.067ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	44.280s	22.179ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	44.280s	22.179ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	10.430s	4.501ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
- Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
  - 0.sysrst_ctrl_ec_pwr_on_rst.109376688304826861142115564024763577738195943235421321975703930274287427758496
    Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 2741459107 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 2741459107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 1 failures:

Test sysrst_ctrl_ultra_low_pwr has 1 failures.

0.sysrst_ctrl_ultra_low_pwr.69239224155540218132754476130659925292321760125439769033482280263554416900156
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2128807238 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 3331307238 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3331307238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---