UART Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: c0fece9

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	22.660s	11.605ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.650s	75.171us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.620s	38.511us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.910s	127.535us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.740s	20.508us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.090s	33.080us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.620s	38.511us	1	1	100.00
		uart_csr_aliasing	1.740s	20.508us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	15.680s	13.531ms	1	1	100.00
V2	parity	uart_smoke	22.660s	11.605ms	1	1	100.00
		uart_tx_rx	15.680s	13.531ms	1	1	100.00
V2	parity_error	uart_intr	53.620s	36.986ms	1	1	100.00
		uart_rx_parity_err	22.940s	63.337ms	1	1	100.00
V2	watermark	uart_tx_rx	15.680s	13.531ms	1	1	100.00
		uart_intr	53.620s	36.986ms	1	1	100.00
V2	fifo_full	uart_fifo_full	31.930s	104.811ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	56.650s	84.627ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	2.442m	126.479ms	1	1	100.00
V2	rx_frame_err	uart_intr	53.620s	36.986ms	1	1	100.00
V2	rx_break_err	uart_intr	53.620s	36.986ms	1	1	100.00
V2	rx_timeout	uart_intr	53.620s	36.986ms	1	1	100.00
V2	perf	uart_perf	2.059m	14.818ms	1	1	100.00
V2	sys_loopback	uart_loopback	18.830s	11.513ms	1	1	100.00
V2	line_loopback	uart_loopback	18.830s	11.513ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	7.390s	4.865ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.650s	4.288ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	3.680s	907.910us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.750s	6.133ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.291m	111.374ms	1	1	100.00
V2	stress_all	uart_stress_all	44.030s	51.015ms	1	1	100.00
V2	alert_test	uart_alert_test	1.550s	51.049us	1	1	100.00
V2	intr_test	uart_intr_test	1.490s	21.008us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.230s	160.441us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.230s	160.441us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.650s	75.171us	1	1	100.00
		uart_csr_rw	1.620s	38.511us	1	1	100.00
		uart_csr_aliasing	1.740s	20.508us	1	1	100.00
		uart_same_csr_outstanding	1.580s	18.768us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.650s	75.171us	1	1	100.00
		uart_csr_rw	1.620s	38.511us	1	1	100.00
		uart_csr_aliasing	1.740s	20.508us	1	1	100.00
		uart_same_csr_outstanding	1.580s	18.768us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.970s	112.493us	1	1	100.00
		uart_tl_intg_err	2.680s	150.836us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.680s	150.836us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	27.680s	8.898ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.25901415962987290093605688579447509842628449265101517154899650844065260593916
      Line 70, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 2527064662 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
        UVM_ERROR @ 2527075079 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 2527168832 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (27 [0x1b] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 2651641565 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 2651641565 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0