CHIP Simulation Results

Monday June 16 2025 18:36:32 UTC

GitHub Revision: `c0fece9`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.112m	3.105ms	1	1	100.00
		chip_sw_example_rom	1.229m	2.267ms	1	1	100.00
		chip_sw_example_manufacturer	2.311m	2.947ms	1	1	100.00
		chip_sw_example_concurrency	1.759m	2.541ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.623m	7.276ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.244m	4.445ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.156m	3.996ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	50.981m	25.792ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	4.221m	5.797ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	50.981m	25.792ms	1	1	100.00
		chip_csr_rw	3.244m	4.445ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.930s	197.033us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	3.945m	3.861ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	3.945m	3.861ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	3.945m	3.861ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.256m	4.059ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.256m	4.059ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.038m	4.622ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.513m	4.328ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.265m	4.008ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.178m	8.378ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.419m	9.076ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.996m	3.662ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	3.312m	5.927ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.312m	5.927ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	1.969m	3.194ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.406m	3.135ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.368m	3.457ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	3.707m	4.854ms	1	1	100.00
		chip_tap_straps_testunlock0	4.714m	5.591ms	1	1	100.00
		chip_tap_straps_rma	1.568m	2.389ms	1	1	100.00
		chip_tap_straps_prod	7.566m	8.415ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.711m	2.525ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.332m	8.419ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	4.981m	4.537ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	4.981m	4.537ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.221m	8.486ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	36.723m	23.416ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.304m	4.022ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.356m	6.340ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.725m	18.112ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.619m	2.461ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.300m	7.117ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.684m	3.237ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.959m	10.811ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.807m	3.173ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.961m	5.180ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.924m	2.321ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.210m	2.949ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	6.965m	7.109ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.426m	5.655ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.559m	3.439ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.426m	5.655ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.699m	2.581ms	1	1	100.00
		chip_sw_aes_smoketest	2.314m	3.100ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.398m	3.150ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.629m	3.582ms	1	1	100.00
		chip_sw_csrng_smoketest	2.108m	3.140ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.632m	3.680ms	1	1	100.00
		chip_sw_gpio_smoketest	2.324m	3.077ms	1	1	100.00
		chip_sw_hmac_smoketest	3.344m	3.821ms	1	1	100.00
		chip_sw_kmac_smoketest	2.324m	2.685ms	1	1	100.00
		chip_sw_otbn_smoketest	16.410m	9.065ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.290m	4.861ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.602m	6.217ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.927m	2.737ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.677m	2.760ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.910m	2.706ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.824m	2.792ms	1	1	100.00
		chip_sw_uart_smoketest	2.922m	3.111ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.700m	2.672ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	6.001m	5.240ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.926h	60.790ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	39.164m	14.783ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.238m	6.323ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.925m	3.466ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.563m	3.271ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.800h	53.842ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.938h	56.965ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	38.190s	1.797ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	38.190s	1.797ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	50.981m	25.792ms	1	1	100.00
		chip_same_csr_outstanding	40.249m	29.823ms	1	1	100.00
		chip_csr_hw_reset	3.623m	7.276ms	1	1	100.00
		chip_csr_rw	3.244m	4.445ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	50.981m	25.792ms	1	1	100.00
		chip_same_csr_outstanding	40.249m	29.823ms	1	1	100.00
		chip_csr_hw_reset	3.623m	7.276ms	1	1	100.00
		chip_csr_rw	3.244m	4.445ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	1.214m	2.607ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.360s	39.595us	1	1	100.00
		xbar_smoke_large_delays	44.060s	7.291ms	1	1	100.00
		xbar_smoke_slow_rsp	51.750s	5.534ms	1	1	100.00
		xbar_random_zero_delays	28.600s	595.268us	1	1	100.00
		xbar_random_large_delays	48.370s	7.366ms	1	1	100.00
		xbar_random_slow_rsp	3.029m	23.354ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	32.520s	1.270ms	1	1	100.00
		xbar_error_and_unmapped_addr	28.140s	1.098ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	13.300s	493.587us	1	1	100.00
		xbar_error_and_unmapped_addr	28.140s	1.098ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.216m	3.714ms	1	1	100.00
		xbar_access_same_device_slow_rsp	8.024m	59.210ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	19.200s	1.043ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.344m	11.222ms	1	1	100.00
		xbar_stress_all_with_error	1.286m	1.671ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.904m	1.327ms	1	1	100.00
		xbar_stress_all_with_reset_error	1.146m	358.260us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	39.164m	14.783ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	31.583m	22.813ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	40.454m	15.006ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.471m	10.453ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	39.735m	15.023ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.380m	14.806ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.699m	15.724ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	38.608m	14.995ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.820s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.230s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	20.000s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	18.000s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.210s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.080s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.640s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.170s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.060s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.320s	10.220us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.510s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	15.490s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.910s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.290s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.570s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.590s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.600s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.300s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	15.670s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	15.540s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.890s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.330s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.590s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.250s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	16.700s	10.160us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.265m	11.413ms	1	1	100.00
		rom_e2e_asm_init_dev	38.565m	15.532ms	1	1	100.00
		rom_e2e_asm_init_prod	39.091m	16.210ms	1	1	100.00
		rom_e2e_asm_init_prod_end	37.217m	15.576ms	1	1	100.00
		rom_e2e_asm_init_rma	35.854m	15.503ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.145m	15.369ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	36.744m	14.899ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	35.408m	15.006ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	39.192m	15.829ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.601m	34.265ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.601m	34.265ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.184m	3.166ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.619m	2.461ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.437m	2.828ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.141m	3.259ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	20.879m	10.907ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.529m	2.641ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.170m	5.293ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.497m	5.751ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.939m	5.494ms	1	1	100.00
		chip_plic_all_irqs_10	4.020m	3.601ms	1	1	100.00
		chip_plic_all_irqs_20	4.988m	4.588ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.128m	3.924ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	19.630m	12.753ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	2.869m	2.593ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	1.488m	2.410ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.238m	10.955ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.923m	7.305ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.667m	7.405ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	12.894m	8.117ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.170h	256.372ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.069m	4.402ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.290m	4.861ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.069m	4.402ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.077m	7.507ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.077m	7.507ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.127m	7.629ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.193m	5.487ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.199m	6.180ms	1	1	100.00
		chip_sw_aes_idle	2.141m	3.259ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.958m	3.375ms	1	1	100.00
		chip_sw_kmac_idle	2.580m	2.964ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.320m	4.038ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.661m	3.931ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.978m	4.488ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.721m	4.174ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	9.606m	9.112ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.908m	4.150ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.958m	4.607ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.883m	3.808ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.626m	4.952ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	4.957m	3.664ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.185m	4.917ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.221m	8.486ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	6.165m	9.799ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.883m	3.808ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.626m	4.952ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.304m	4.022ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.356m	6.340ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.725m	18.112ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.619m	2.461ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	10.300m	7.117ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.684m	3.237ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.959m	10.811ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.807m	3.173ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.961m	5.180ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.924m	2.321ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.123m	2.942ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.614m	4.132ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.234m	7.236ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.395m	24.145ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.790m	2.721ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.343m	3.570ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	19.040m	11.678ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.879m	3.574ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.893m	4.771ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	21.013m	24.840ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.265h	100.897ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.221m	8.486ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.735m	4.097ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.917m	3.496ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.497m	5.751ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.923m	7.305ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	18.464m	7.675ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.267m	2.487ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.407m	6.327ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.836m	3.147ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.221h	29.370ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.797m	2.602ms	1	1	100.00
		chip_sw_edn_entropy_reqs	8.021m	6.323ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.797m	2.602ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	18.464m	7.675ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.814m	2.538ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.005m	19.227ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.486m	5.912ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.356m	6.340ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.091m	3.961ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.304m	4.022ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	55.463m	43.405ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.005m	19.227ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.947m	3.823ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	26.491m	13.691ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.537m	4.828ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	55.463m	43.405ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.537m	4.828ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.537m	4.828ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.537m	4.828ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.537m	4.828ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.497m	5.751ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.561m	4.270ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.025m	5.250ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.037m	6.296ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.037m	6.296ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	1.925m	2.360ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.684m	3.237ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.958m	3.375ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.212m	3.776ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.580m	4.265ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	4.949m	4.683ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.163m	5.381ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.758m	4.532ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.381m	4.218ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	26.491m	13.691ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	18.959m	10.811ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	21.984m	11.597ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	20.879m	10.907ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	30.833m	10.482ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.018m	2.871ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.521m	2.985ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.807m	3.173ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	26.491m	13.691ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.587m	6.749ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.518m	2.768ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	18.629m	9.740ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.580m	2.964ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.170m	5.293ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	3.707m	4.854ms	1	1	100.00
		chip_tap_straps_rma	1.568m	2.389ms	1	1	100.00
		chip_tap_straps_prod	7.566m	8.415ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.403m	2.713ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.587m	6.749ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.587m	6.749ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.587m	6.749ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	16.570m	8.489ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.537m	4.828ms	1	1	100.00
		chip_sw_flash_rma_unlocked	55.463m	43.405ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.160m	3.549ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.796m	6.111ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.448m	5.601ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.183m	8.486ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.587m	6.749ms	1	1	100.00
		chip_sw_keymgr_key_derivation	26.491m	13.691ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.590m	8.485ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	7.443m	8.782ms	1	1	100.00
		chip_prim_tl_access	1.561m	4.270ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	6.165m	9.799ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.908m	4.150ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.958m	4.607ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.883m	3.808ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.626m	4.952ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	4.957m	3.664ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.185m	4.917ms	1	1	100.00
		chip_tap_straps_dev	3.707m	4.854ms	1	1	100.00
		chip_tap_straps_rma	1.568m	2.389ms	1	1	100.00
		chip_tap_straps_prod	7.566m	8.415ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.977m	22.147ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.224m	3.056ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.403m	2.898ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.287m	3.755ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.300m	3.639ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	20.636m	35.799ms	1	1	100.00
		chip_rv_dm_lc_disabled	6.977m	22.147ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.019h	48.803ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.022h	48.502ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.413m	9.634ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	58.987m	47.764ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	20.636m	35.799ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.106m	2.275ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.023m	3.079ms	1	1	100.00
		rom_volatile_raw_unlock	1.024m	1.972ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	53.681m	15.984ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	52.725m	18.112ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.199m	6.180ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.199m	6.180ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.199m	6.180ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.361m	3.813ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.587m	6.749ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.005m	19.227ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.361m	3.813ms	1	1	100.00
		chip_sw_keymgr_key_derivation	26.491m	13.691ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.686m	3.748ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.131m	2.966ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.005m	19.227ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.361m	3.813ms	1	1	100.00
		chip_sw_keymgr_key_derivation	26.491m	13.691ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.686m	3.748ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.131m	2.966ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.587m	6.749ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	3.683m	5.693ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.403m	2.713ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.160m	3.549ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.796m	6.111ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.448m	5.601ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.183m	8.486ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.587m	6.749ms	1	1	100.00
		chip_prim_tl_access	1.561m	4.270ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.561m	4.270ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.974m	8.601ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.790m	6.456ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	14.912m	23.997ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.802m	7.735ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	8.505m	10.128ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.586m	7.118ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.961m	23.745ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.483m	12.976ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.077m	7.507ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	12.055m	12.548ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.291m	4.798ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.790m	6.456ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.143m	4.906ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	38.227m	41.899ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.666m	5.906ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.758m	5.120ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	28.704m	28.709ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.819m	8.198ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	13.714m	9.112ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	24.539m	29.020ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.032m	3.214ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.497m	5.751ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.590m	8.485ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.590m	8.485ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	13.714m	9.112ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	28.704m	28.709ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	6.291m	4.798ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.290m	4.861ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.374m	4.821ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.558m	5.154ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.481m	4.207ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	19.630m	12.753ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.067m	2.998ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.497m	5.751ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.667m	7.405ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.231m	5.579ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.936m	5.230ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.733m	3.230ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.131m	2.966ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.558m	5.154ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.558m	5.154ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	15.970m	12.039ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	13.037m	13.923ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.374m	4.821ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.725m	4.110ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.044m	7.000ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.568m	2.389ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.977m	22.147ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.939m	5.494ms	1	1	100.00
		chip_plic_all_irqs_10	4.020m	3.601ms	1	1	100.00
		chip_plic_all_irqs_20	4.988m	4.588ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.379m	2.638ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.207m	2.262ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	39.164m	14.783ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.111m	6.132ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.576m	2.346ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.642m	3.619ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.796m	2.908ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.686m	3.748ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.961m	5.180ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.168m	8.306ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.866m	8.562ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	7.443m	8.782ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.497m	5.751ms	1	1	100.00
		chip_sw_data_integrity_escalation	4.981m	4.537ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.819m	8.198ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	17.591m	25.570ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.956m	3.266ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.097m	3.542ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.768m	4.912ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	17.591m	25.570ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	17.591m	25.570ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	36.699m	20.518ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	36.699m	20.518ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.680m	6.389ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	49.601m	34.265ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.965m	2.651ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.856m	3.353ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.916m	3.817ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.506m	3.953ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	15.957m	7.600ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.359h	32.024ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.169m	12.095ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.841m	3.349ms	1	1	100.00
V2		TOTAL			241	275	87.64
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.380m	3.060ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	1.241m	2.190ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.366h	72.388ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.891m	3.362ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	15.897m	11.105ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.854m	12.188ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.389m	11.326ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.132m	3.098ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.630m	3.905ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.464m	4.956ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.386s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.754m	4.635ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.653m	2.826ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	10.280m	4.786ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	13.566m	6.600ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.193m	2.391ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.700m	4.971ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.750m	2.417ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.522m	4.783ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.393m	4.769ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.008m	3.587ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	13.714m	9.112ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	15.897m	11.105ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.854m	12.188ms	1	1	100.00
		rom_e2e_jtag_debug_rma	15.389m	11.326ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.320m	4.957ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.497m	5.751ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.367h	38.520ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.367h	38.520ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	3.020m	4.156ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.256m	4.059ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	50.720m	18.023ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.513m	2.888ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.628m	4.535ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.839m	2.877ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.471m	2.379ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.030m	3.906ms	0	1	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.763s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.079m	2.810ms	1	1	100.00
		TOTAL			287	325	88.31

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.40823873492492475306238845252640002752823922197120943185292914315005041678253
    Line 607, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.84220688970416265399915963193326435715854118524736265102036998771746536059249
    Line 630, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.86508966768511272779261668804504872671201237508997188073557147108662714836776
    Line 732, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.80080954924617679016914992302123189665403159964185870502747838520847503007203
    Line 690, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.77591190090222802953616002711503069955053655601721838915271494753159147659671
    Line 645, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.11640958017625962861736816838086588718969903955618549149265638292681009148415
    Line 610, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.63095760400566832529602729580575281313829736109690108281146362966645797384711
    Line 610, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.54428944781856560229949398032488197327625023271643165312824075072536282428869
    Line 600, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4457149003260401320035027146980113555188547363984016379904222643064159691438
    Line 610, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.76098904840400919294460919197747097081606633707676415806518903987932144322074
    Line 597, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.91990427793041234923795691251796616825329500431209052203153506169884460026701
    Line 691, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.45308909802639512043199635445742934527089037599167844320548370026392991778264
    Line 761, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2068885863549687356825008168850533139420927094165805291275762321152112842307
    Line 747, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.21040569491610617464950400773873705446909530127217849654398457237080575722439
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.139s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.62067694648976942776828386492889220055542814705732037764638453464982621341491
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 2.571s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.93232127790103958068880110829905694767914232919919399152588110777518220470746
    Line 997, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.77538800158438207295120974584194886650964614949861559812602553532340324326141
    Line 628, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.32431101513062811907207830436498144871654135914984473379504335602317679958652
    Line 825, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.35814592859070059447111812992499046382987155667652529426985436697000155224480
    Line 715, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.43106625311277773940431417016226096782763993402403510774905334428185097283246
    Line 425, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2346.461400 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2346.461400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98971) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.115775971561184268156346579830356985760960182660131468081149785598186063417222
Line 450, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 5154.414814 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@98971) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5154.414814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.20339983993102416264280026326757235930701378348981280676588666235993820013401
    Line 469, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34264.705187 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34264.705187 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.90594948377331307296759878090541513701981603102282420224387490543293390592866
    Line 404, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2641.052980 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2641.052980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.46214344795634998002916123479388077420036408976253071780200403644114323501748
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2410.322090 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2410.322090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.72493891652843985434273816090447719030193741149952125617075328504059954760900
    Line 416, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2486.860647 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2486.860647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33271) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.72120203801832857652926795120989435016526481238949662160412533066834631827497
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1797.390720 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33271) { a_addr: 'h10384  a_data: 'h31962e02  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h4  a_user: 'h1b6a6  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1797.390720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 1 failures:
- Test chip_sw_pwrmgr_lowpower_cancel has 1 failures.
  - 0.chip_sw_pwrmgr_lowpower_cancel.15829801484190053821906196569362350274693309177792963155335365903889717846966
    Line 417, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
```
  UVM_ERROR @ 3905.860876 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
  UVM_INFO @ 3905.860876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.105741130672411777174271368417439944764051020251547372848069209641120430306096
    Line 409, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3465.800000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3465.800000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.85676949028038072827558818714447986642299638634302823877521661287061847811549
    Line 424, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3271.100000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3271.100000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.20515772845754602515982329156682953324369430041931420222331583067027299255373
    Line 486, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3361.718966 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3361.718966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.84658799701054771194262061479570735548610200721526874479011331201194924928880
    Line 687, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.61497523260157982718029844564355998241126830469695658769435379344804532093697
    Line 692, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```