ADC_CTRL Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	11.870s	6.135ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.340s	1.373ms	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.170s	405.341us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	23.950s	51.685ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.420s	1.019ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.460s	447.564us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.170s	405.341us	1	1	100.00
		adc_ctrl_csr_aliasing	3.420s	1.019ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	4.835m	328.695ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.228m	168.298ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.727m	326.717ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	1.043m	160.544ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	4.799m	193.820ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	6.108m	203.951ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	7.209m	516.474ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.703m	330.764ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	6.150s	3.521ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	16.300s	33.849ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.759m	114.532ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	8.498m	396.218ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	2.240s	410.400us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	2.330s	484.392us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.500s	814.527us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.500s	814.527us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.340s	1.373ms	1	1	100.00
		adc_ctrl_csr_rw	2.170s	405.341us	1	1	100.00
		adc_ctrl_csr_aliasing	3.420s	1.019ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	9.380s	4.716ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.340s	1.373ms	1	1	100.00
		adc_ctrl_csr_rw	2.170s	405.341us	1	1	100.00
		adc_ctrl_csr_aliasing	3.420s	1.019ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	9.380s	4.716ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	5.640s	8.217ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.780s	4.368ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.780s	4.368ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	5.300s	9.246ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00