HMAC Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 3.080s 1.203ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.640s 82.015us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.630s 19.805us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.980s 1.422ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.060s 445.571us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.680s 48.148us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.630s 19.805us 1 1 100.00
hmac_csr_aliasing 7.060s 445.571us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 48.270s 4.858ms 1 1 100.00
V2 back_pressure hmac_back_pressure 5.210s 416.580us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.000m 25.236ms 1 1 100.00
hmac_test_sha384_vectors 19.770s 948.709us 1 1 100.00
hmac_test_sha512_vectors 19.690s 954.447us 1 1 100.00
hmac_test_hmac256_vectors 10.190s 686.484us 1 1 100.00
hmac_test_hmac384_vectors 7.160s 828.645us 1 1 100.00
hmac_test_hmac512_vectors 13.490s 1.550ms 1 1 100.00
V2 burst_wr hmac_burst_wr 14.820s 2.170ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 3.126m 1.382ms 1 1 100.00
V2 error hmac_error 8.570s 568.045us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 46.610s 13.898ms 1 1 100.00
V2 save_and_restore hmac_smoke 3.080s 1.203ms 1 1 100.00
hmac_long_msg 48.270s 4.858ms 1 1 100.00
hmac_back_pressure 5.210s 416.580us 1 1 100.00
hmac_datapath_stress 3.126m 1.382ms 1 1 100.00
hmac_burst_wr 14.820s 2.170ms 1 1 100.00
hmac_stress_all 10.423m 5.088ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 3.080s 1.203ms 1 1 100.00
hmac_long_msg 48.270s 4.858ms 1 1 100.00
hmac_back_pressure 5.210s 416.580us 1 1 100.00
hmac_datapath_stress 3.126m 1.382ms 1 1 100.00
hmac_wipe_secret 46.610s 13.898ms 1 1 100.00
hmac_test_sha256_vectors 3.000m 25.236ms 1 1 100.00
hmac_test_sha384_vectors 19.770s 948.709us 1 1 100.00
hmac_test_sha512_vectors 19.690s 954.447us 1 1 100.00
hmac_test_hmac256_vectors 10.190s 686.484us 1 1 100.00
hmac_test_hmac384_vectors 7.160s 828.645us 1 1 100.00
hmac_test_hmac512_vectors 13.490s 1.550ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 3.080s 1.203ms 1 1 100.00
hmac_long_msg 48.270s 4.858ms 1 1 100.00
hmac_back_pressure 5.210s 416.580us 1 1 100.00
hmac_datapath_stress 3.126m 1.382ms 1 1 100.00
hmac_burst_wr 14.820s 2.170ms 1 1 100.00
hmac_error 8.570s 568.045us 1 1 100.00
hmac_wipe_secret 46.610s 13.898ms 1 1 100.00
hmac_test_sha256_vectors 3.000m 25.236ms 1 1 100.00
hmac_test_sha384_vectors 19.770s 948.709us 1 1 100.00
hmac_test_sha512_vectors 19.690s 954.447us 1 1 100.00
hmac_test_hmac256_vectors 10.190s 686.484us 1 1 100.00
hmac_test_hmac384_vectors 7.160s 828.645us 1 1 100.00
hmac_test_hmac512_vectors 13.490s 1.550ms 1 1 100.00
hmac_stress_all 10.423m 5.088ms 1 1 100.00
V2 stress_all hmac_stress_all 10.423m 5.088ms 1 1 100.00
V2 alert_test hmac_alert_test 1.500s 10.556us 1 1 100.00
V2 intr_test hmac_intr_test 1.430s 63.407us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.080s 182.445us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.080s 182.445us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.640s 82.015us 1 1 100.00
hmac_csr_rw 1.630s 19.805us 1 1 100.00
hmac_csr_aliasing 7.060s 445.571us 1 1 100.00
hmac_same_csr_outstanding 2.140s 24.152us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.640s 82.015us 1 1 100.00
hmac_csr_rw 1.630s 19.805us 1 1 100.00
hmac_csr_aliasing 7.060s 445.571us 1 1 100.00
hmac_same_csr_outstanding 2.140s 24.152us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.680s 93.376us 1 1 100.00
hmac_tl_intg_err 2.190s 191.987us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.190s 191.987us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 3.080s 1.203ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.440s 661.676us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.837m 33.428ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 4.840s 281.346us 1 1 100.00
TOTAL 28 28 100.00