I2C Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: `b69339b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	21.660s	1.841ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	21.420s	3.605ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.890s	60.120us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.680s	17.703us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.520s	1.976ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.640s	42.475us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.640s	26.487us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.680s	17.703us	1	1	100.00
		i2c_csr_aliasing	2.640s	42.475us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.210s	1.763ms	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	2.846m	30.730ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.290m	18.466ms	1	1	100.00
V2	host_override	i2c_host_override	1.620s	48.925us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.078m	15.640ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	56.810s	2.750ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.010s	106.839us	1	1	100.00
		i2c_host_fifo_fmt_empty	9.580s	497.148us	1	1	100.00
		i2c_host_fifo_reset_rx	7.220s	579.202us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	54.800s	3.064ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	11.620s	2.630ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.920s	80.326us	1	1	100.00
V2	target_glitch	i2c_target_glitch	7.460s	2.205ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	25.930s	5.363ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.630s	953.566us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	41.690s	2.620ms	1	1	100.00
		i2c_target_intr_smoke	4.300s	702.347us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.400s	408.000us	1	1	100.00
		i2c_target_fifo_reset_tx	2.770s	530.850us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	1.930m	52.394ms	1	1	100.00
		i2c_target_stress_rd	41.690s	2.620ms	1	1	100.00
		i2c_target_intr_stress_wr	19.720s	22.747ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.980s	1.274ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	6.530s	2.063ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.760s	903.969us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	14.080s	10.027ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.470s	216.352us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.300s	377.360us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.290m	18.466ms	1	1	100.00
		i2c_host_perf_precise	2.050s	99.176us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	11.620s	2.630ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.460s	461.923us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.210s	3.466ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.890s	570.831us	1	1	100.00
		i2c_target_nack_txstretch	2.670s	738.721us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	8.020s	1.820ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.530s	459.797us	1	1	100.00
V2	alert_test	i2c_alert_test	1.710s	15.959us	1	1	100.00
V2	intr_test	i2c_intr_test	1.590s	25.579us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.820s	103.816us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.820s	103.816us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.890s	60.120us	1	1	100.00
		i2c_csr_rw	1.680s	17.703us	1	1	100.00
		i2c_csr_aliasing	2.640s	42.475us	1	1	100.00
		i2c_same_csr_outstanding	1.880s	109.249us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.890s	60.120us	1	1	100.00
		i2c_csr_rw	1.680s	17.703us	1	1	100.00
		i2c_csr_aliasing	2.640s	42.475us	1	1	100.00
		i2c_same_csr_outstanding	1.880s	109.249us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.600s	63.772us	1	1	100.00
		i2c_sec_cm	1.770s	86.635us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.600s	63.772us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	22.230s	1.096ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.190s	234.502us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	36.090s	12.871ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.28513036529322089506117165727619169446432476434470210212328651903179717929270
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1095622259 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1095622259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.108309605788443329575301689908377688888973037320061842792232370653390953555352
    Line 158, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12870798900 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12870798900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.106631833254864286066149717482427241433496232331781567014670237520990768490117
Line 329, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 30729597715 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5631428

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.65422296311981138578195307017890136381843588369365078381393601633176289303695
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 234502277 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 234502277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.30610475263578963833740584121210816480749427475514349090657120990481390404937
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10027084651 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10027084651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```