KEYMGR Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.710s	343.309us	1	1	100.00
V1	random	keymgr_random	4.600s	102.418us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.080s	17.414us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.330s	85.342us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.560s	137.512us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	13.580s	492.367us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.610s	41.317us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.330s	85.342us	1	1	100.00
		keymgr_csr_aliasing	13.580s	492.367us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	9.580s	874.566us	1	1	100.00
V2	sideload	keymgr_sideload	4.050s	281.364us	1	1	100.00
		keymgr_sideload_kmac	5.590s	1.024ms	1	1	100.00
		keymgr_sideload_aes	3.040s	417.108us	1	1	100.00
		keymgr_sideload_otbn	15.820s	2.506ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.160s	53.529us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.740s	66.056us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.320s	124.107us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	16.810s	922.818us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	4.490s	128.622us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.970s	337.412us	1	1	100.00
V2	stress_all	keymgr_stress_all	22.780s	4.717ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.810s	37.924us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.540s	37.921us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.020s	155.038us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.020s	155.038us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.080s	17.414us	1	1	100.00
		keymgr_csr_rw	2.330s	85.342us	1	1	100.00
		keymgr_csr_aliasing	13.580s	492.367us	1	1	100.00
		keymgr_same_csr_outstanding	2.120s	191.226us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.080s	17.414us	1	1	100.00
		keymgr_csr_rw	2.330s	85.342us	1	1	100.00
		keymgr_csr_aliasing	13.580s	492.367us	1	1	100.00
		keymgr_same_csr_outstanding	2.120s	191.226us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
		keymgr_tl_intg_err	5.300s	1.022ms	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	8.990s	512.565us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	8.990s	512.565us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	8.990s	512.565us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	8.990s	512.565us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	7.760s	238.636us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.300s	1.022ms	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	8.990s	512.565us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	9.580s	874.566us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.600s	102.418us	1	1	100.00
		keymgr_csr_rw	2.330s	85.342us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.600s	102.418us	1	1	100.00
		keymgr_csr_rw	2.330s	85.342us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.600s	102.418us	1	1	100.00
		keymgr_csr_rw	2.330s	85.342us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.740s	66.056us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	4.490s	128.622us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	4.490s	128.622us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.600s	102.418us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	4.940s	265.460us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.780s	81.902us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.740s	66.056us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.780s	81.902us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.780s	81.902us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.780s	81.902us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.950s	1.110ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.780s	81.902us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	13.030s	1.654ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.108247392642243280851139591465689155759680578271922358353268578276306432035872
      Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
        UVM_ERROR @  41316970 ps: (keymgr_csr_assert_fpv.sv:400) [ASSERT FAILED] sealing_sw_binding_0_rd_A
        UVM_INFO @  41316970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---