KMAC/MASKED Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	21.290s	746.772us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.820s	32.870us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.820s	35.075us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.760s	640.899us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.020s	2.944ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.600s	35.017us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.820s	35.075us	1	1	100.00
		kmac_csr_aliasing	7.020s	2.944ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.710s	20.879us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.110s	134.490us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	8.878m	7.070ms	1	1	100.00
V2	burst_write	kmac_burst_write	9.650m	75.319ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.760s	12.557ms	1	1	100.00
		kmac_test_vectors_sha3_256	21.619m	19.773ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.750s	3.550ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.947m	40.956ms	1	1	100.00
		kmac_test_vectors_shake_128	3.112m	13.796ms	1	1	100.00
		kmac_test_vectors_shake_256	5.529m	302.553ms	1	1	100.00
		kmac_test_vectors_kmac	3.540s	218.974us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.340s	200.432us	1	1	100.00
V2	sideload	kmac_sideload	1.322m	1.283ms	1	1	100.00
V2	app	kmac_app	1.706m	16.753ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.582m	6.129ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.495m	5.636ms	1	1	100.00
V2	error	kmac_error	2.487m	10.543ms	1	1	100.00
V2	key_error	kmac_key_error	7.510s	935.011us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.920s	319.409us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.850s	35.428us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.060s	32.306us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	16.410s	4.643ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.740s	47.554us	1	1	100.00
V2	stress_all	kmac_stress_all	14.216m	70.026ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.530s	44.081us	1	1	100.00
V2	alert_test	kmac_alert_test	1.810s	52.168us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.140s	132.176us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.140s	132.176us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.820s	32.870us	1	1	100.00
		kmac_csr_rw	1.820s	35.075us	1	1	100.00
		kmac_csr_aliasing	7.020s	2.944ms	1	1	100.00
		kmac_same_csr_outstanding	2.570s	402.775us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.820s	32.870us	1	1	100.00
		kmac_csr_rw	1.820s	35.075us	1	1	100.00
		kmac_csr_aliasing	7.020s	2.944ms	1	1	100.00
		kmac_same_csr_outstanding	2.570s	402.775us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.320s	273.014us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.320s	273.014us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.320s	273.014us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.320s	273.014us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.940s	14.330us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	54.500s	20.775ms	1	1	100.00
		kmac_tl_intg_err	2.750s	213.389us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.750s	213.389us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.740s	47.554us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	21.290s	746.772us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.322m	1.283ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.320s	273.014us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	54.500s	20.775ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	54.500s	20.775ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	54.500s	20.775ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	21.290s	746.772us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.740s	47.554us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	54.500s	20.775ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.181m	12.201ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	21.290s	746.772us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.495m	3.981ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.87282758207592911773461734166902475957430442437725054850495935775976237007691
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
        UVM_ERROR @  14329813 ps: (kmac_csr_assert_fpv.sv:554) [ASSERT FAILED] prefix_9_rd_A
        UVM_INFO @  14329813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---