KMAC/UNMASKED Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	16.540s	1.073ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.920s	18.407us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.970s	85.559us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.850s	3.455ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.230s	197.463us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.250s	43.795us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.970s	85.559us	1	1	100.00
		kmac_csr_aliasing	4.230s	197.463us	1	1	100.00
V1	mem_walk	kmac_mem_walk	2.000s	170.713us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.830s	52.119us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	2.591m	10.506ms	1	1	100.00
V2	burst_write	kmac_burst_write	7.058m	17.362ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.320s	4.565ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.290s	1.696ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.500s	5.397ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.960s	4.149ms	1	1	100.00
		kmac_test_vectors_shake_128	1.534m	2.205ms	1	1	100.00
		kmac_test_vectors_shake_256	4.027m	85.866ms	1	1	100.00
		kmac_test_vectors_kmac	2.900s	126.053us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.550s	69.195us	1	1	100.00
V2	sideload	kmac_sideload	1.891m	33.286ms	1	1	100.00
V2	app	kmac_app	1.123m	1.892ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.979m	27.222ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	52.730s	6.260ms	1	1	100.00
V2	error	kmac_error	19.260s	352.324us	1	1	100.00
V2	key_error	kmac_key_error	2.320s	809.639us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.750s	666.764us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	29.200s	8.473ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	24.820s	524.431us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	32.720s	6.513ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.190s	152.305us	1	1	100.00
V2	stress_all	kmac_stress_all	11.969m	16.892ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.750s	49.801us	1	1	100.00
V2	alert_test	kmac_alert_test	1.730s	22.826us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.700s	57.868us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.700s	57.868us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.920s	18.407us	1	1	100.00
		kmac_csr_rw	1.970s	85.559us	1	1	100.00
		kmac_csr_aliasing	4.230s	197.463us	1	1	100.00
		kmac_same_csr_outstanding	2.430s	26.789us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.920s	18.407us	1	1	100.00
		kmac_csr_rw	1.970s	85.559us	1	1	100.00
		kmac_csr_aliasing	4.230s	197.463us	1	1	100.00
		kmac_same_csr_outstanding	2.430s	26.789us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.420s	173.420us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.420s	173.420us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.420s	173.420us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.420s	173.420us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.810s	17.736us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	16.760s	5.068ms	1	1	100.00
		kmac_tl_intg_err	2.780s	198.365us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.780s	198.365us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.190s	152.305us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	16.540s	1.073ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.891m	33.286ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.420s	173.420us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	16.760s	5.068ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	16.760s	5.068ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	16.760s	5.068ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	16.540s	1.073ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.190s	152.305us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	16.760s	5.068ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	57.870s	4.565ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	16.540s	1.073ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	41.250s	10.642ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.98397154191120221385044088037274092180366973459539616574519754354758822435925
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @  17736170 ps: (kmac_csr_assert_fpv.sv:536) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @  17736170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---