OTBN Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	13.000s	46.562us	1	1	100.00
V1	single_binary	otbn_single	9.000s	17.592us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	35.807us	1	1	100.00
V1	csr_rw	otbn_csr_rw	7.000s	15.487us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	96.932us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	25.595us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	9.000s	22.696us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	15.487us	1	1	100.00
		otbn_csr_aliasing	6.000s	25.595us	1	1	100.00
V1	mem_walk	otbn_mem_walk	33.000s	527.243us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	127.872us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	22.000s	260.219us	1	1	100.00
V2	multi_error	otbn_multi_err	53.000s	150.991us	1	1	100.00
V2	back_to_back	otbn_multi	51.000s	276.672us	1	1	100.00
V2	stress_all	otbn_stress_all	1.233m	245.660us	1	1	100.00
V2	lc_escalation	otbn_escalate	8.000s	25.053us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	26.085us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	13.000s	27.252us	1	1	100.00
V2	alert_test	otbn_alert_test	8.000s	20.508us	1	1	100.00
V2	intr_test	otbn_intr_test	32.000s	22.794us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	39.000s	255.111us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	39.000s	255.111us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	35.807us	1	1	100.00
		otbn_csr_rw	7.000s	15.487us	1	1	100.00
		otbn_csr_aliasing	6.000s	25.595us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	25.959us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	35.807us	1	1	100.00
		otbn_csr_rw	7.000s	15.487us	1	1	100.00
		otbn_csr_aliasing	6.000s	25.595us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	25.959us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	12.000s	25.252us	1	1	100.00
		otbn_dmem_err	11.000s	77.993us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	24.000s	167.963us	1	1	100.00
		otbn_controller_ispr_rdata_err	8.000s	87.865us	1	1	100.00
		otbn_mac_bignum_acc_err	13.000s	40.423us	1	1	100.00
		otbn_urnd_err	10.000s	29.280us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	85.380us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	1.050m	10.002ms	0	1	0.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	41.990us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
		otbn_tl_intg_err	45.000s	128.583us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	52.000s	105.225us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	13.000s	46.562us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	11.000s	77.993us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	12.000s	25.252us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	45.000s	128.583us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	8.000s	25.053us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	12.000s	25.252us	1	1	100.00
		otbn_dmem_err	11.000s	77.993us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	26.085us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	85.380us	1	1	100.00
		otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	9.000s	17.592us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	12.000s	25.252us	1	1	100.00
		otbn_dmem_err	11.000s	77.993us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	26.085us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	85.380us	1	1	100.00
		otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	8.000s	25.053us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	12.000s	25.252us	1	1	100.00
		otbn_dmem_err	11.000s	77.993us	1	1	100.00
		otbn_zero_state_err_urnd	10.000s	26.085us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	85.380us	1	1	100.00
		otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	9.000s	17.592us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	7.000s	56.951us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	13.143us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	25.000s	112.761us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	25.000s	112.761us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	8.000s	30.776us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	61.422us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	326.958us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	9.000s	326.958us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	7.000s	10.100us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	9.000s	17.592us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	9.000s	17.592us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	9.000s	17.592us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	51.000s	276.672us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	9.000s	17.592us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	9.000s	17.592us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	8.000s	41.199us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	9.000s	17.592us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.000m	2.319ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.383m	1.749ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.56933177941836726973551225524842238475935860042229627922612467193314628601311
      Line 317, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1749332761 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1749332761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_mem_gnt_acc_err_vseq.sv:41) [otbn_mem_gnt_acc_err_vseq] timeout occurred! has 1 failures:

  • Test otbn_mem_gnt_acc_err has 1 failures.

    • 0.otbn_mem_gnt_acc_err.32724435149594766514756993268179618975895170101321768006122263795543636061980
      Line 108, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_mem_gnt_acc_err/latest/run.log

        UVM_FATAL @ 10002083750 ps: (otbn_mem_gnt_acc_err_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.otbn_mem_gnt_acc_err_vseq] timeout occurred!
        UVM_INFO @ 10002083750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---