ROM_CTRL/32KB Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.550s 235.182us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.720s 407.993us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.040s 143.273us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.200s 169.748us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.940s 146.542us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.860s 137.886us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.040s 143.273us 1 1 100.00
rom_ctrl_csr_aliasing 4.940s 146.542us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.280s 164.157us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.610s 538.803us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.240s 315.081us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 13.940s 683.787us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.470s 576.410us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.020s 372.668us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.950s 440.761us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.950s 440.761us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.720s 407.993us 1 1 100.00
rom_ctrl_csr_rw 4.040s 143.273us 1 1 100.00
rom_ctrl_csr_aliasing 4.940s 146.542us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.260s 1.081ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.720s 407.993us 1 1 100.00
rom_ctrl_csr_rw 4.040s 143.273us 1 1 100.00
rom_ctrl_csr_aliasing 4.940s 146.542us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.260s 1.081ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 45.300s 19.098ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 20.200s 850.180us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.447m 507.315us 1 1 100.00
rom_ctrl_tl_intg_err 21.870s 365.224us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.447m 507.315us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.447m 507.315us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 45.300s 19.098ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 45.300s 19.098ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 45.300s 19.098ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 45.300s 19.098ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 45.300s 19.098ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.447m 507.315us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.447m 507.315us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.550s 235.182us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.550s 235.182us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.550s 235.182us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.870s 365.224us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 45.300s 19.098ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.470s 576.410us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 45.300s 19.098ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 45.300s 19.098ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 45.300s 19.098ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 20.200s 850.180us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.447m 507.315us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.014m 6.036ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00