RV_DM/USE_JTAG_INTERFACE Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 5.160s 3.762ms 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 2.280s 724.699us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.640s 149.923us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 4.890s 8.536ms 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 2.550s 1.012ms 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 2.310s 1.456ms 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 3.780s 4.596ms 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 23.490s 67.347ms 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.327m 50.177ms 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.790s 215.659us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.720s 109.317us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.710s 167.238us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.880s 99.863us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.710s 168.458us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.790s 776.910us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 1.550s 83.157us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 2.250s 483.905us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.790s 215.659us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.670s 144.908us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 2.320s 788.682us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.710s 167.238us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 1.770s 206.327us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 3.050s 269.480us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 2.690s 452.572us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 24.240s 10.707ms 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 43.440s 5.615ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 1.740s 124.534us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 43.440s 5.615ms 1 1 100.00
rv_dm_csr_rw 2.690s 452.572us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 1.660s 53.883us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 1.600s 41.987us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 5.160s 3.762ms 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.690s 252.551us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 1.650s 151.543us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 1.720s 133.730us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.850s 577.401us 1 1 100.00
V2 sba rv_dm_sba_tl_access 3.220s 734.520us 1 1 100.00
rv_dm_delayed_resp_sba_tl_access 2.300s 426.627us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 3.180s 980.377us 1 1 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 17.390s 8.336ms 1 1 100.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 2.030s 618.751us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 4.550s 4.854ms 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 2.010s 374.505us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 2.090s 313.180us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 16.710s 10.599ms 0 1 0.00
rv_dm_tap_fsm_rand_reset 2.110s 99.560us 0 1 0.00
V2 hartsel_warl rv_dm_hartsel_warl 1.630s 97.121us 1 1 100.00
V2 stress_all rv_dm_stress_all 5.030s 2.699ms 1 1 100.00
V2 alert_test rv_dm_alert_test 1.730s 26.677us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 1.850s 41.855us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 1.850s 41.855us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 43.440s 5.615ms 1 1 100.00
rv_dm_csr_hw_reset 3.050s 269.480us 1 1 100.00
rv_dm_csr_rw 2.690s 452.572us 1 1 100.00
rv_dm_same_csr_outstanding 3.890s 317.105us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 43.440s 5.615ms 1 1 100.00
rv_dm_csr_hw_reset 3.050s 269.480us 1 1 100.00
rv_dm_csr_rw 2.690s 452.572us 1 1 100.00
rv_dm_same_csr_outstanding 3.890s 317.105us 1 1 100.00
V2 TOTAL 15 19 78.95
V2S tl_intg_err rv_dm_sec_cm 5.150s 1.635ms 1 1 100.00
rv_dm_tl_intg_err 13.650s 2.180ms 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 13.650s 2.180ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 4.550s 4.854ms 1 1 100.00
rv_dm_debug_disabled 1.760s 58.467us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 4.550s 4.854ms 1 1 100.00
rv_dm_debug_disabled 1.760s 58.467us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 5.160s 3.762ms 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.930s 157.961us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.960s 140.175us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 1.960s 140.175us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.930s 157.961us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 2.380s 192.757us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 1.640s 24.970us 1 1 100.00
TOTAL 47 53 88.68

Failure Buckets