| V1 |
random |
rv_timer_random |
1.610s |
27.249us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.500s |
37.504us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.540s |
13.987us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
2.800s |
249.420us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.640s |
18.510us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
1.670s |
29.645us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.540s |
13.987us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.640s |
18.510us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
1.500s |
93.098us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
2.260s |
629.568us |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
1.720s |
336.460us |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
1.720s |
336.460us |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
2.300s |
3.660ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.520s |
15.467us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.570s |
132.516us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
2.710s |
350.828us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
2.710s |
350.828us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.500s |
37.504us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.540s |
13.987us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.640s |
18.510us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.520s |
27.576us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.500s |
37.504us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.540s |
13.987us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.640s |
18.510us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.520s |
27.576us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.750s |
306.851us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
1.780s |
175.097us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
1.780s |
175.097us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.580s |
66.861us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.510s |
32.400us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
6.380s |
609.589us |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |