SPI_DEVICE/1R1W Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.220s	3.408ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.060s	175.418us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.410s	103.347us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.610s	1.245ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.590s	926.927us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.610s	284.075us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.410s	103.347us	1	1	100.00
		spi_device_csr_aliasing	15.590s	926.927us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.560s	26.684us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.490s	46.126us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.630s	19.940us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.540s	3.719us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.680s	3.617us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.950s	70.229us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.950s	70.229us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	15.400s	9.235ms	1	1	100.00
		spi_device_tpm_sts_read	1.580s	81.228us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	4.830s	1.804ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.900s	650.239us	1	1	100.00
		spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.880s	14.201ms	1	1	100.00
		spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.880s	14.201ms	1	1	100.00
		spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	11.860s	6.359ms	1	1	100.00
		spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	11.860s	6.359ms	1	1	100.00
		spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	11.860s	6.359ms	1	1	100.00
		spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	11.860s	6.359ms	1	1	100.00
		spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	11.860s	6.359ms	1	1	100.00
		spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.090s	117.776us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	11.550s	1.382ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	11.550s	1.382ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	11.550s	1.382ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	28.290s	7.929ms	1	1	100.00
		spi_device_read_buffer_direct	4.910s	744.659us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	11.550s	1.382ms	1	1	100.00
		spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	39.560s	17.076ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.070s	919.240us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.070s	919.240us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.220s	3.408ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	40.040s	12.047ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.042m	17.200ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.660s	15.434us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.650s	34.021us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.790s	268.456us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.790s	268.456us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.060s	175.418us	1	1	100.00
		spi_device_csr_rw	2.410s	103.347us	1	1	100.00
		spi_device_csr_aliasing	15.590s	926.927us	1	1	100.00
		spi_device_same_csr_outstanding	3.770s	353.229us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.060s	175.418us	1	1	100.00
		spi_device_csr_rw	2.410s	103.347us	1	1	100.00
		spi_device_csr_aliasing	15.590s	926.927us	1	1	100.00
		spi_device_same_csr_outstanding	3.770s	353.229us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.200s	247.503us	1	1	100.00
		spi_device_tl_intg_err	16.000s	964.380us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.000s	964.380us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.510m	24.546ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.25364545063268225781129587925785244113566245728447746215031254711441860023393
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2398958 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[16])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2398958 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2398958 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[912])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.82079444778796539253484763571111070012333511402450891875862671815984787185509
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1213983 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbbd491 [101110111101010010010001] vs 0x0 [0])
        UVM_ERROR @   1242983 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x100f59 [100000000111101011001] vs 0x0 [0])
        UVM_ERROR @   1333983 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x25eb21 [1001011110101100100001] vs 0x0 [0])
        UVM_ERROR @   1350983 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1cc865 [111001100100001100101] vs 0x0 [0])
        UVM_ERROR @   1433983 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6d0de1 [11011010000110111100001] vs 0x0 [0])