SPI_DEVICE/2P Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 1.142m 10.658ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 2.220s 139.179us 1 1 100.00
V1 csr_rw spi_device_csr_rw 2.590s 149.369us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 18.510s 1.948ms 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 14.950s 315.858us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 4.100s 87.693us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 2.590s 149.369us 1 1 100.00
spi_device_csr_aliasing 14.950s 315.858us 1 1 100.00
V1 mem_walk spi_device_mem_walk 1.720s 42.492us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 2.540s 536.089us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 1.640s 24.868us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.780s 31.530us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 1.600s 31.474us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 2.510s 111.276us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 2.510s 111.276us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 4.940s 10.163ms 1 1 100.00
spi_device_tpm_sts_read 1.520s 19.890us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 14.030s 1.483ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 3.760s 1.297ms 1 1 100.00
spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 23.140s 12.728ms 1 1 100.00
spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 23.140s 12.728ms 1 1 100.00
spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 cmd_read_status spi_device_intercept 6.710s 439.208us 1 1 100.00
spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 6.710s 439.208us 1 1 100.00
spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 6.710s 439.208us 1 1 100.00
spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 cmd_fast_read spi_device_intercept 6.710s 439.208us 1 1 100.00
spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 6.710s 439.208us 1 1 100.00
spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 flash_cmd_upload spi_device_upload 2.850s 62.288us 1 1 100.00
V2 mailbox_command spi_device_mailbox 12.200s 955.718us 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 12.200s 955.718us 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 12.200s 955.718us 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 11.270s 4.073ms 1 1 100.00
spi_device_read_buffer_direct 9.560s 3.230ms 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 12.200s 955.718us 1 1 100.00
spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 quad_spi spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 dual_spi spi_device_flash_all 3.264m 81.789ms 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 2.800s 115.391us 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 2.800s 115.391us 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 1.142m 10.658ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 5.854m 72.437ms 1 1 100.00
V2 stress_all spi_device_stress_all 1.710m 20.974ms 1 1 100.00
V2 alert_test spi_device_alert_test 1.600s 34.811us 1 1 100.00
V2 intr_test spi_device_intr_test 1.540s 12.412us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.800s 368.673us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.800s 368.673us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 2.220s 139.179us 1 1 100.00
spi_device_csr_rw 2.590s 149.369us 1 1 100.00
spi_device_csr_aliasing 14.950s 315.858us 1 1 100.00
spi_device_same_csr_outstanding 4.020s 364.704us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 2.220s 139.179us 1 1 100.00
spi_device_csr_rw 2.590s 149.369us 1 1 100.00
spi_device_csr_aliasing 14.950s 315.858us 1 1 100.00
spi_device_same_csr_outstanding 4.020s 364.704us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 1.870s 64.130us 1 1 100.00
spi_device_tl_intg_err 6.750s 1.066ms 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 6.750s 1.066ms 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 1.674m 41.325ms 1 1 100.00
TOTAL 33 33 100.00