SPI_HOST Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	59.000s	4.839ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	3.000s	25.033us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	71.396us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	207.697us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	22.765us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	41.350us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	71.396us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.765us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	14.856us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	40.318us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	11.000s	59.147us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	10.000s	186.895us	1	1	100.00
		spi_host_error_cmd	8.000s	16.732us	1	1	100.00
		spi_host_event	8.000s	387.477us	1	1	100.00
V2	clock_rate	spi_host_speed	13.000s	98.214us	1	1	100.00
V2	speed	spi_host_speed	13.000s	98.214us	1	1	100.00
V2	chip_select_timing	spi_host_speed	13.000s	98.214us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	11.000s	163.074us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	86.426us	1	1	100.00
V2	cpol_cpha	spi_host_speed	13.000s	98.214us	1	1	100.00
V2	full_cycle	spi_host_speed	13.000s	98.214us	1	1	100.00
V2	duplex	spi_host_smoke	59.000s	4.839ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	59.000s	4.839ms	1	1	100.00
V2	stress_all	spi_host_stress_all	29.900m	1.000s	0	1	0.00
V2	spien	spi_host_spien	6.000s	603.207us	1	1	100.00
V2	stall	spi_host_status_stall	48.000s	5.069ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	390.202us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	10.000s	186.895us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	56.865us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	32.776us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	353.312us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	353.312us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	3.000s	25.033us	1	1	100.00
		spi_host_csr_rw	4.000s	71.396us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.765us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	18.001us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	3.000s	25.033us	1	1	100.00
		spi_host_csr_rw	4.000s	71.396us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.765us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	18.001us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_tl_intg_err	5.000s	104.450us	1	1	100.00
		spi_host_sec_cm	3.000s	64.256us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	5.000s	104.450us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.017m	8.754ms	1	1	100.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_stress_all has 1 failures.

    • 0.spi_host_stress_all.13864682441790820609251870183925942090546795473873294005257367401915479645651
      Line 148, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---