SRAM_CTRL/MAIN Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	5.990s	691.729us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.500s	32.812us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.490s	74.771us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.040s	432.104us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.760s	57.302us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.270s	376.690us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.490s	74.771us	1	1	100.00
		sram_ctrl_csr_aliasing	1.760s	57.302us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.825m	13.830ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	47.050s	957.135us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.850m	16.383ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.376m	3.718ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	19.805m	132.959ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.270m	140.326ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	59.390s	13.690ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.310m	87.296ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.740s	8.452ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.119m	25.688ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	48.510s	763.767us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	10.470s	6.874ms	1	1	100.00
		sram_ctrl_throughput_w_readback	5.310s	2.736ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	5.746m	9.348ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.010s	1.397ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	11.935m	102.092ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.720s	14.060us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.500s	76.346us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.500s	76.346us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.500s	32.812us	1	1	100.00
		sram_ctrl_csr_rw	1.490s	74.771us	1	1	100.00
		sram_ctrl_csr_aliasing	1.760s	57.302us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.720s	66.420us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.500s	32.812us	1	1	100.00
		sram_ctrl_csr_rw	1.490s	74.771us	1	1	100.00
		sram_ctrl_csr_aliasing	1.760s	57.302us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.720s	66.420us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	33.120s	28.167ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.620s	2.734us	0	1	0.00
		sram_ctrl_tl_intg_err	2.830s	214.906us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.620s	2.734us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.830s	214.906us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	5.746m	9.348ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	5.746m	9.348ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.490s	74.771us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.310m	87.296ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.310m	87.296ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.310m	87.296ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	59.390s	13.690ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.560s	2.786ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	33.120s	28.167ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.180s	699.481us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	5.990s	691.729us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	5.990s	691.729us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.310m	87.296ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.620s	2.734us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	59.390s	13.690ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.620s	2.734us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.620s	2.734us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	5.990s	691.729us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.620s	2.734us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	6.210s	1.495ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.28256746549559551718791863444283391371099249981060354254150505288836868305983
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2733518 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2733518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---