SYSRST_CTRL Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	4.530s	2.111ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	5.860s	2.480ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.500s	2.229ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	2.670s	2.371ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	9.360s	4.016ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	5.520s	2.038ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	29.070s	73.176ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	7.390s	3.337ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	3.560s	2.078ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	5.520s	2.038ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.390s	3.337ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	1.151m	72.578ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	1.052m	36.608ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	7.530s	3.020ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	6.080s	3.136ms	0	1	0.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	6.430s	2.515ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	3.400s	2.223ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	7.290s	3.064ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	6.510s	2.611ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	6.130s	6.550ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	15.100s	31.403ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	2.078m	149.785ms	0	1	0.00
V2	alert_test	sysrst_ctrl_alert_test	2.200s	2.062ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	2.210s	2.038ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	4.870s	2.270ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	4.870s	2.270ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	9.360s	4.016ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.520s	2.038ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.390s	3.337ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	17.480s	8.439ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	9.360s	4.016ms	1	1	100.00
		sysrst_ctrl_csr_rw	5.520s	2.038ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	7.390s	3.337ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	17.480s	8.439ms	1	1	100.00
V2		TOTAL			12	15	80.00
V2S	tl_intg_err	sysrst_ctrl_sec_cm	16.180s	42.154ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	21.390s	42.853ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	21.390s	42.853ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	9.540s	4.589ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	27	88.89

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 3 failures:

  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.21946088073219902030046860844745604995742880783583477987247716911040093923457
      Line 380, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 6550143471 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 6550173470 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 6550173470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test sysrst_ctrl_edge_detect has 1 failures.

    • 0.sysrst_ctrl_edge_detect.43864235481881915126526209079185303605495161140019091357527887493906215013362
      Line 383, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest/run.log

        UVM_ERROR @ 3136429244 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 3136459546 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 3136459546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test sysrst_ctrl_stress_all has 1 failures.

    • 0.sysrst_ctrl_stress_all.18569382794327423074651305166072484240521551240082597955548271785648873627657
      Line 427, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 149784826321 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 149784888819 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 149784888819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---