UART Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: b69339b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.500s	487.507us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.540s	60.325us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.430s	12.487us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.410s	56.120us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.470s	18.980us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.680s	91.921us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.430s	12.487us	1	1	100.00
		uart_csr_aliasing	1.470s	18.980us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	46.170s	143.428ms	1	1	100.00
V2	parity	uart_smoke	2.500s	487.507us	1	1	100.00
		uart_tx_rx	46.170s	143.428ms	1	1	100.00
V2	parity_error	uart_intr	22.540s	12.270ms	1	1	100.00
		uart_rx_parity_err	7.200m	200.907ms	1	1	100.00
V2	watermark	uart_tx_rx	46.170s	143.428ms	1	1	100.00
		uart_intr	22.540s	12.270ms	1	1	100.00
V2	fifo_full	uart_fifo_full	16.590s	48.603ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	41.390s	35.525ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	11.600s	119.950ms	1	1	100.00
V2	rx_frame_err	uart_intr	22.540s	12.270ms	1	1	100.00
V2	rx_break_err	uart_intr	22.540s	12.270ms	1	1	100.00
V2	rx_timeout	uart_intr	22.540s	12.270ms	1	1	100.00
V2	perf	uart_perf	8.519m	15.336ms	1	1	100.00
V2	sys_loopback	uart_loopback	11.740s	10.145ms	1	1	100.00
V2	line_loopback	uart_loopback	11.740s	10.145ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	11.740s	37.262ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.020s	515.710us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	9.100s	7.371ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	25.960s	4.642ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.432m	156.679ms	1	1	100.00
V2	stress_all	uart_stress_all	1.016m	250.885ms	1	1	100.00
V2	alert_test	uart_alert_test	1.530s	13.745us	1	1	100.00
V2	intr_test	uart_intr_test	1.470s	50.838us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.600s	197.692us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.600s	197.692us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.540s	60.325us	1	1	100.00
		uart_csr_rw	1.430s	12.487us	1	1	100.00
		uart_csr_aliasing	1.470s	18.980us	1	1	100.00
		uart_same_csr_outstanding	1.450s	17.830us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.540s	60.325us	1	1	100.00
		uart_csr_rw	1.430s	12.487us	1	1	100.00
		uart_csr_aliasing	1.470s	18.980us	1	1	100.00
		uart_same_csr_outstanding	1.450s	17.830us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.960s	62.372us	1	1	100.00
		uart_tl_intg_err	1.780s	185.119us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.780s	185.119us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	28.150s	13.133ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.31988773289356089064189189778278708675071453491356595578679684206939551665590
      Line 71, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 34326439399 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 34327397740 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 34331481106 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 34338731164 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 34387939891 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0