CHIP Simulation Results

Tuesday June 17 2025 18:40:16 UTC

GitHub Revision: `b69339b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.651m	2.631ms	1	1	100.00
		chip_sw_example_rom	59.230s	2.993ms	1	1	100.00
		chip_sw_example_manufacturer	1.506m	2.558ms	1	1	100.00
		chip_sw_example_concurrency	1.605m	2.548ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.386m	4.991ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.429m	5.152ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.408m	4.028ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.018h	28.771ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	45.450s	2.209ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.018h	28.771ms	1	1	100.00
		chip_csr_rw	3.429m	5.152ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	8.320s	171.315us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.390m	4.075ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.390m	4.075ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.390m	4.075ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.903m	4.700ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.903m	4.700ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.660m	4.514ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	4.737m	4.348ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	5.976m	4.463ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	3.875m	3.604ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	14.744m	8.205ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	3.855m	4.427ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	2.877m	4.664ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.877m	4.664ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.287m	3.347ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.447m	6.077ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.831m	3.079ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	6.338m	8.337ms	1	1	100.00
		chip_tap_straps_testunlock0	7.676m	7.786ms	1	1	100.00
		chip_tap_straps_rma	6.253m	6.635ms	1	1	100.00
		chip_tap_straps_prod	14.960m	14.578ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.424m	2.860ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	11.744m	9.319ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.141m	4.394ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.141m	4.394ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.079m	7.687ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	32.013m	19.831ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.063m	3.965ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.559m	6.205ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.608m	18.729ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.780m	2.813ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.883m	5.508ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.175m	3.324ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.933m	12.432ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.367m	3.162ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.817m	4.521ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.351m	2.193ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.408m	3.527ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	4.915m	6.081ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.253m	5.142ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.464m	3.356ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.253m	5.142ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.542m	2.559ms	1	1	100.00
		chip_sw_aes_smoketest	2.090m	2.609ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.528m	3.309ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.715m	3.363ms	1	1	100.00
		chip_sw_csrng_smoketest	1.951m	2.613ms	1	1	100.00
		chip_sw_entropy_src_smoketest	4.672m	3.823ms	1	1	100.00
		chip_sw_gpio_smoketest	3.429m	3.473ms	1	1	100.00
		chip_sw_hmac_smoketest	3.293m	2.681ms	1	1	100.00
		chip_sw_kmac_smoketest	2.435m	2.890ms	1	1	100.00
		chip_sw_otbn_smoketest	16.931m	9.999ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.694m	5.401ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.647m	6.531ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.450m	2.453ms	1	1	100.00
		chip_sw_rv_timer_smoketest	1.846m	2.417ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.339m	2.432ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.497m	2.238ms	1	1	100.00
		chip_sw_uart_smoketest	2.560m	3.192ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.661m	2.921ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.180m	4.152ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.982h	61.283ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	38.559m	14.294ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.597m	6.569ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.532m	3.182ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.830m	3.496ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.800h	53.842ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.901h	56.497ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	51.620s	2.251ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	51.620s	2.251ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.018h	28.771ms	1	1	100.00
		chip_same_csr_outstanding	18.865m	14.369ms	1	1	100.00
		chip_csr_hw_reset	2.386m	4.991ms	1	1	100.00
		chip_csr_rw	3.429m	5.152ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.018h	28.771ms	1	1	100.00
		chip_same_csr_outstanding	18.865m	14.369ms	1	1	100.00
		chip_csr_hw_reset	2.386m	4.991ms	1	1	100.00
		chip_csr_rw	3.429m	5.152ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	26.340s	1.346ms	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.890s	57.000us	1	1	100.00
		xbar_smoke_large_delays	50.840s	8.281ms	1	1	100.00
		xbar_smoke_slow_rsp	52.430s	5.829ms	1	1	100.00
		xbar_random_zero_delays	30.570s	564.465us	1	1	100.00
		xbar_random_large_delays	4.970m	49.745ms	1	1	100.00
		xbar_random_slow_rsp	3.474m	24.991ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	28.580s	979.056us	1	1	100.00
		xbar_error_and_unmapped_addr	23.520s	972.215us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	21.580s	1.132ms	1	1	100.00
		xbar_error_and_unmapped_addr	23.520s	972.215us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	28.420s	874.134us	1	1	100.00
		xbar_access_same_device_slow_rsp	2.511m	17.910ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	6.290s	62.300us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.651m	4.239ms	1	1	100.00
		xbar_stress_all_with_error	2.430m	3.421ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.024m	584.401us	1	1	100.00
		xbar_stress_all_with_reset_error	4.966m	7.249ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.559m	14.294ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	35.636m	28.226ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	37.893m	15.175ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.854m	10.786ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.132m	15.080ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	40.995m	15.993ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	39.760m	15.719ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.358m	15.008ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.870s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.840s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.640s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.630s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	16.770s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	21.650s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.510s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	20.250s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.520s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.190s	10.160us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.160s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.420s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.940s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.490s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.670s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.640s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.420s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.480s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	15.640s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	15.890s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.000s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.170s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.280s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.790s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.020s	10.180us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	28.695m	11.626ms	1	1	100.00
		rom_e2e_asm_init_dev	39.187m	16.084ms	1	1	100.00
		rom_e2e_asm_init_prod	36.921m	14.846ms	1	1	100.00
		rom_e2e_asm_init_prod_end	36.816m	15.735ms	1	1	100.00
		rom_e2e_asm_init_rma	36.837m	14.250ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	36.509m	15.264ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	35.896m	14.440ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	36.288m	15.256ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	38.825m	15.761ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.462m	34.589ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.462m	34.589ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.614m	2.846ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.780m	2.813ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.338m	2.433ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.157m	2.379ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	20.809m	10.040ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.418m	3.089ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.099m	5.163ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.747m	5.223ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	7.880m	5.712ms	1	1	100.00
		chip_plic_all_irqs_10	3.938m	3.374ms	1	1	100.00
		chip_plic_all_irqs_20	6.147m	4.410ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.218m	3.750ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.740m	11.173ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	2.641m	3.572ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.007m	2.774ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.207m	11.492ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.061m	8.319ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.086m	7.753ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	11.973m	7.473ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.197h	255.247ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	2.864m	3.628ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	2.694m	5.401ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	2.864m	3.628ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.736m	10.091ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	9.736m	10.091ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.971m	7.434ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.173m	6.052ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.187m	6.254ms	1	1	100.00
		chip_sw_aes_idle	2.157m	2.379ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.612m	3.324ms	1	1	100.00
		chip_sw_kmac_idle	1.778m	3.063ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.532m	3.574ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.782m	4.797ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.760m	5.417ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	2.929m	3.914ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	12.682m	11.934ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.096m	3.205ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.681m	4.837ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.293m	3.738ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.304m	4.099ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.413m	3.393ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.558m	4.244ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.079m	7.687ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	7.876m	13.079ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.293m	3.738ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.304m	4.099ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.063m	3.965ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.559m	6.205ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.608m	18.729ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.780m	2.813ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.883m	5.508ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.175m	3.324ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.933m	12.432ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.367m	3.162ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.817m	4.521ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.351m	2.193ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.930m	3.243ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.848m	4.971ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.352m	7.581ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.359m	25.015ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.254m	2.686ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.455m	3.524ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	7.923m	6.164ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.687m	3.057ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.715m	5.203ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	15.548m	21.890ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.913h	141.629ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.079m	7.687ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.613m	4.625ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.558m	3.509ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.747m	5.223ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	18.061m	8.319ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.372m	6.476ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.851m	2.524ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	5.348m	4.912ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.771m	2.719ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.204h	28.311ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	1.663m	2.269ms	1	1	100.00
		chip_sw_edn_entropy_reqs	13.424m	7.695ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	1.663m	2.269ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.372m	6.476ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.961m	2.463ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	21.872m	25.210ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	7.897m	5.763ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.559m	6.205ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.604m	4.471ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.063m	3.965ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	55.607m	44.999ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	21.872m	25.210ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.731m	4.139ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	22.723m	10.740ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.116m	4.537ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	55.607m	44.999ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.116m	4.537ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.116m	4.537ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.116m	4.537ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.116m	4.537ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.747m	5.223ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.355m	12.067ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.082m	5.442ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	5.416m	5.815ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	5.416m	5.815ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.756m	3.675ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.175m	3.324ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.612m	3.324ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.772m	3.958ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.723m	3.290ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.654m	5.306ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.532m	4.696ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.234m	5.155ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.188m	3.936ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	22.723m	10.740ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	24.933m	12.432ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	16.796m	9.476ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	20.809m	10.040ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	39.617m	14.204ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.069m	2.736ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.377m	3.038ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.367m	3.162ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	22.723m	10.740ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.094m	7.260ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.553m	2.907ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	16.777m	8.189ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.778m	3.063ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.099m	5.163ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	6.338m	8.337ms	1	1	100.00
		chip_tap_straps_rma	6.253m	6.635ms	1	1	100.00
		chip_tap_straps_prod	14.960m	14.578ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.364m	2.720ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.094m	7.260ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.094m	7.260ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.094m	7.260ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	16.222m	9.575ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.116m	4.537ms	1	1	100.00
		chip_sw_flash_rma_unlocked	55.607m	44.999ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.007m	2.696ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.234m	6.544ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.127m	5.805ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.019m	7.026ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.094m	7.260ms	1	1	100.00
		chip_sw_keymgr_key_derivation	22.723m	10.740ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.510m	9.477ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	5.980m	9.003ms	1	1	100.00
		chip_prim_tl_access	4.355m	12.067ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	7.876m	13.079ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	5.096m	3.205ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.681m	4.837ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.293m	3.738ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.304m	4.099ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.413m	3.393ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	5.558m	4.244ms	1	1	100.00
		chip_tap_straps_dev	6.338m	8.337ms	1	1	100.00
		chip_tap_straps_rma	6.253m	6.635ms	1	1	100.00
		chip_tap_straps_prod	14.960m	14.578ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.251m	11.550ms	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.373m	3.060ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.375m	2.847ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.156m	2.988ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.787m	3.475ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.511m	30.054ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.251m	11.550ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.069h	51.834ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	56.449m	48.039ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	6.986m	9.260ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	57.136m	46.333ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.511m	30.054ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	52.380s	2.325ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.022m	2.210ms	1	1	100.00
		rom_volatile_raw_unlock	58.890s	2.925ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	52.316m	16.038ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	55.608m	18.729ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.187m	6.254ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.187m	6.254ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.187m	6.254ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.918m	3.170ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.094m	7.260ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	21.872m	25.210ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.918m	3.170ms	1	1	100.00
		chip_sw_keymgr_key_derivation	22.723m	10.740ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.333m	4.388ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.586m	2.982ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	21.872m	25.210ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.918m	3.170ms	1	1	100.00
		chip_sw_keymgr_key_derivation	22.723m	10.740ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.333m	4.388ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.586m	2.982ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.094m	7.260ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	4.013m	5.267ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.364m	2.720ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.007m	2.696ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.234m	6.544ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.127m	5.805ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	8.019m	7.026ms	1	1	100.00
		chip_sw_lc_ctrl_transition	5.094m	7.260ms	1	1	100.00
		chip_prim_tl_access	4.355m	12.067ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.355m	12.067ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	15.808m	9.579ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.192m	5.936ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.282m	25.519ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.802m	7.964ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.599m	9.203ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	4.464m	6.541ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	16.324m	26.371ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.367m	13.064ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	9.736m	10.091ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	14.074m	12.330ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.352m	3.843ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.192m	5.936ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.202m	5.474ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	34.994m	35.322ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.699m	6.527ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.717m	5.664ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	23.554m	27.156ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.922m	7.795ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.475m	12.756ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.805m	29.033ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.370m	2.871ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.747m	5.223ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.510m	9.477ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.510m	9.477ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.475m	12.756ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	23.554m	27.156ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.352m	3.843ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	2.694m	5.401ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.956m	5.093ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	2.880m	3.722ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.181m	4.551ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.740m	11.173ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.725m	3.369ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.747m	5.223ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.086m	7.753ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.979m	5.024ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.736m	4.631ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.690m	2.649ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.586m	2.982ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	2.880m	3.722ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	2.880m	3.722ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	8.313m	9.210ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.873m	13.882ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.956m	5.093ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.842m	3.489ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.574m	5.769ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	6.253m	6.635ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.251m	11.550ms	1	1	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	7.880m	5.712ms	1	1	100.00
		chip_plic_all_irqs_10	3.938m	3.374ms	1	1	100.00
		chip_plic_all_irqs_20	6.147m	4.410ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.807m	3.340ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.120m	3.496ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	38.559m	14.294ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.250m	8.381ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.688m	3.334ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.115m	4.043ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.037m	2.390ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.333m	4.388ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.817m	4.521ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	6.894m	7.456ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	4.936m	7.224ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	5.980m	9.003ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.747m	5.223ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.141m	4.394ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.922m	7.795ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.190m	22.675ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.691m	2.875ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.101m	3.047ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	6.255m	4.695ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.190m	22.675ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.190m	22.675ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	39.604m	21.137ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	39.604m	21.137ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	2.899m	5.134ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	46.462m	34.589ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.382m	2.668ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.596m	2.662ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.591m	4.029ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.284m	4.140ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.768m	7.772ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.195h	31.617ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.678m	12.022ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.541m	3.313ms	1	1	100.00
V2		TOTAL			240	275	87.27
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.550m	3.171ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.203m	3.018ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.435h	71.648ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.513m	5.906ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.042m	12.146ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.157m	11.555ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.463m	10.271ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.133m	4.975ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.322m	4.781ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.173m	4.796ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.946s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.182m	5.343ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.062m	2.866ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	12.198m	5.467ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	17.012m	8.394ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	2.900m	2.319ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	8.321m	5.106ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.774m	2.605ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.325m	5.348ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.253m	6.272ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.365m	5.538ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.475m	12.756ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.042m	12.146ms	1	1	100.00
		rom_e2e_jtag_debug_dev	16.157m	11.555ms	1	1	100.00
		rom_e2e_jtag_debug_rma	17.463m	10.271ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	4.689m	3.990ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.747m	5.223ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.409h	38.840ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.409h	38.840ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.710m	2.916ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.903m	4.700ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	45.830m	18.660ms	1	1	100.00
V3		TOTAL			22	23	95.65
	Unmapped tests	chip_sival_flash_info_access	2.075m	2.887ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.511m	4.980ms	1	1	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.509m	2.739ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.940m	2.464ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.074m	3.708ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	9.862s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.128m	3.074ms	1	1	100.00
		TOTAL			286	325	88.00

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.23068274449452177611715948537420306330029176825790084394454013292417848257427
    Line 707, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.39604095742839951427521279666967091016778593028777747155214695995131498054015
    Line 752, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.100095167917764290912861225698524008379660653275714646804051223103454432496964
    Line 636, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.92178656350060463350650906794675172056152844001407227490316309090425590580182
    Line 654, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.20081745351407941595951293595022702894805799599564353562855817231279596661333
    Line 788, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.7343356527622581891575213837238492750003488260514394060198248947508415755735
    Line 683, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.49736806090922545981879894326769553748045564835584682490914511282407796044104
    Line 658, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.46598534301972935277907798604241001887857053261971529233752252367132562265842
    Line 729, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.103087475895308150088921623723659665409789902113787379269495117900673569524868
    Line 655, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.38364202461186396557480417057136072487205071072578006005923758221711876284413
    Line 675, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.89182117189285171554423943656516175384291607690383003944719593169123468527346
    Line 722, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.78095622314400604720707630435642007945615448375943907796806563919316945344776
    Line 704, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.99904992356096636134651922341320519960297757795075899598528458070393726556542
    Line 742, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.95704437899417252673755237179940625419904431615062173882793342252653711297803
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/runs/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.153s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.87409577622325900623038997100900857904777060124569350619231413668500159837640
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/runs/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 1.595s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.29962941564514742686066646692824650841894101289256765163374761724247201879607
    Line 774, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.93704727823695518890033984330126677681255380979460974015917302532542863901744
    Line 674, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.62183577101161589527416579828547752731511543204884979921547709436750455367914
    Line 750, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.60735649804078776691972769837603126788665090083831626803645995267580506511815
    Line 681, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.62387559849406850944827579417433161058036894503402893845362211794394627037274
    Line 526, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3334.407590 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3334.407590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78339) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.14997645501262303575049620560074151219061535541122217077498009119264034177329
Line 450, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3721.896360 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78339) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3721.896360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.64632683278102473627118112062547992134907506855689650595865851939001134959229
    Line 459, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34588.662377 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34588.662377 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.74766286765450857842309295241555730116820421411353210552471267457705601103700
    Line 414, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3088.725980 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 3088.725980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.89720014201659788585848705893654576049912679980111480741264494049912569432216
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2773.738400 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2773.738400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:587) [chip_sw_entropy_src_fuse_vseq] Check failed * == local_alert_agent_cfg.vif.get_alert() (* [*] vs * [*]) Alert usbdev_fatal_fault fired unexpectedly! has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.114506289846437758549927074918966603178470031473877965750609322057584992134636
    Line 411, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2524.497271 us: (cip_base_vseq.sv:587) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] Check failed 0 == local_alert_agent_cfg.vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert usbdev_fatal_fault fired unexpectedly!
  UVM_INFO @ 2524.497271 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31801) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.48898367422879746273124158196511016181224585501546820707806946985846949871041
Line 219, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2250.774630 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31801) { a_addr: 'h10354  a_data: 'h68221c3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h4  a_user: 'h18a7c  d_param: 'h0  d_source: 'h37  d_data: 'h13  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd7d  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2250.774630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.8162158286276177267678189221366096938747994530938427249513667235358343499800
    Line 429, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 3018.097466 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 3018.097466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.8283198155222782896383596550183340202966579945727137593901005703726914368189
    Line 412, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3181.616000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3181.616000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.86453215180894535940603926379696549750665704143233172176157463828518956747309
    Line 421, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3495.585000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3495.585000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.37722992050987036134882573586262605421878563414760507024570900681627838184882
    Line 436, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19830.854104 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19830.854104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.105565955456981495996387882974671462761038667338149757477181041993999309228154
    Line 634, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.42776290588709620716239434004123647791937062199894026758565904752183821332843
    Line 830, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33249) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.108007402644026360534757461938006137024933208102359164016473030943520447021812
Line 226, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2209.343168 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33249) { a_addr: 'h1058c  a_data: 'h7eee5628  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h4  a_user: 'h1ba20  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2209.343168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---