ADC_CTRL Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke adc_ctrl_smoke 13.700s 6.160ms 1 1 100.00
V1 csr_hw_reset adc_ctrl_csr_hw_reset 2.100s 1.355ms 1 1 100.00
V1 csr_rw adc_ctrl_csr_rw 2.020s 471.902us 1 1 100.00
V1 csr_bit_bash adc_ctrl_csr_bit_bash 42.960s 26.921ms 1 1 100.00
V1 csr_aliasing adc_ctrl_csr_aliasing 3.540s 804.857us 1 1 100.00
V1 csr_mem_rw_with_rand_reset adc_ctrl_csr_mem_rw_with_rand_reset 2.590s 502.100us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr adc_ctrl_csr_rw 2.020s 471.902us 1 1 100.00
adc_ctrl_csr_aliasing 3.540s 804.857us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 filters_polled adc_ctrl_filters_polled 8.783m 327.117ms 1 1 100.00
V2 filters_polled_fixed adc_ctrl_filters_polled_fixed 1.210m 162.975ms 1 1 100.00
V2 filters_interrupt adc_ctrl_filters_interrupt 3.681m 504.844ms 1 1 100.00
V2 filters_interrupt_fixed adc_ctrl_filters_interrupt_fixed 2.448m 160.947ms 1 1 100.00
V2 filters_wakeup adc_ctrl_filters_wakeup 8.544m 337.128ms 1 1 100.00
V2 filters_wakeup_fixed adc_ctrl_filters_wakeup_fixed 37.600s 201.979ms 1 1 100.00
V2 filters_both adc_ctrl_filters_both 4.109m 600.000ms 0 1 0.00
V2 clock_gating adc_ctrl_clock_gating 1.970s 1.832ms 0 1 0.00
V2 poweron_counter adc_ctrl_poweron_counter 5.710s 4.517ms 1 1 100.00
V2 lowpower_counter adc_ctrl_lowpower_counter 1.309m 40.932ms 1 1 100.00
V2 fsm_reset adc_ctrl_fsm_reset 23.720s 76.626ms 1 1 100.00
V2 stress_all adc_ctrl_stress_all 15.690s 6.705ms 1 1 100.00
V2 alert_test adc_ctrl_alert_test 2.320s 490.205us 1 1 100.00
V2 intr_test adc_ctrl_intr_test 2.050s 306.199us 1 1 100.00
V2 tl_d_oob_addr_access adc_ctrl_tl_errors 3.020s 626.850us 1 1 100.00
V2 tl_d_illegal_access adc_ctrl_tl_errors 3.020s 626.850us 1 1 100.00
V2 tl_d_outstanding_access adc_ctrl_csr_hw_reset 2.100s 1.355ms 1 1 100.00
adc_ctrl_csr_rw 2.020s 471.902us 1 1 100.00
adc_ctrl_csr_aliasing 3.540s 804.857us 1 1 100.00
adc_ctrl_same_csr_outstanding 12.920s 4.069ms 1 1 100.00
V2 tl_d_partial_access adc_ctrl_csr_hw_reset 2.100s 1.355ms 1 1 100.00
adc_ctrl_csr_rw 2.020s 471.902us 1 1 100.00
adc_ctrl_csr_aliasing 3.540s 804.857us 1 1 100.00
adc_ctrl_same_csr_outstanding 12.920s 4.069ms 1 1 100.00
V2 TOTAL 14 16 87.50
V2S tl_intg_err adc_ctrl_sec_cm 15.270s 7.987ms 1 1 100.00
adc_ctrl_tl_intg_err 4.310s 4.495ms 1 1 100.00
V2S sec_cm_bus_integrity adc_ctrl_tl_intg_err 4.310s 4.495ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset adc_ctrl_stress_all_with_rand_reset 17.070s 3.404ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 23 25 92.00

Failure Buckets