EDN Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.920s	20.286us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.730s	61.806us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.990s	10.934us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.190s	202.221us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.350s	24.341us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.010s	24.294us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.990s	10.934us	1	1	100.00
		edn_csr_aliasing	2.350s	24.341us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.840s	36.687us	1	1	100.00
V2	csrng_commands	edn_genbits	1.840s	36.687us	1	1	100.00
V2	genbits	edn_genbits	1.840s	36.687us	1	1	100.00
V2	interrupts	edn_intr	1.690s	37.063us	1	1	100.00
V2	alerts	edn_alert	1.830s	35.586us	1	1	100.00
V2	errs	edn_err	1.830s	19.284us	1	1	100.00
V2	disable	edn_disable	1.680s	35.225us	1	1	100.00
		edn_disable_auto_req_mode	1.950s	156.906us	1	1	100.00
V2	stress_all	edn_stress_all	2.730s	213.423us	1	1	100.00
V2	intr_test	edn_intr_test	1.910s	50.259us	1	1	100.00
V2	alert_test	edn_alert_test	1.720s	73.931us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.090s	942.642us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.090s	942.642us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.730s	61.806us	1	1	100.00
		edn_csr_rw	1.990s	10.934us	1	1	100.00
		edn_csr_aliasing	2.350s	24.341us	1	1	100.00
		edn_same_csr_outstanding	1.940s	62.717us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.730s	61.806us	1	1	100.00
		edn_csr_rw	1.990s	10.934us	1	1	100.00
		edn_csr_aliasing	2.350s	24.341us	1	1	100.00
		edn_same_csr_outstanding	1.940s	62.717us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.400s	1.858ms	1	1	100.00
		edn_tl_intg_err	2.830s	155.637us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.710s	103.705us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.830s	35.586us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.400s	1.858ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.400s	1.858ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.400s	1.858ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.400s	1.858ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.830s	35.586us	1	1	100.00
		edn_sec_cm	6.400s	1.858ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.830s	35.586us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.830s	155.637us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	8.600s	737.759us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00