952e1dd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | entropy_src_smoke | 4.000s | 23.664us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | entropy_src_csr_hw_reset | 4.000s | 18.856us | 1 | 1 | 100.00 |
| V1 | csr_rw | entropy_src_csr_rw | 4.000s | 71.247us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | entropy_src_csr_bit_bash | 9.000s | 158.360us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | entropy_src_csr_aliasing | 7.000s | 301.005us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | entropy_src_csr_mem_rw_with_rand_reset | 5.000s | 166.610us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | entropy_src_csr_rw | 4.000s | 71.247us | 1 | 1 | 100.00 |
| entropy_src_csr_aliasing | 7.000s | 301.005us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | firmware | entropy_src_smoke | 4.000s | 23.664us | 1 | 1 | 100.00 |
| entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 | ||
| entropy_src_fw_ov | 1.917m | 13.025ms | 1 | 1 | 100.00 | ||
| V2 | firmware_mode | entropy_src_fw_ov | 1.917m | 13.025ms | 1 | 1 | 100.00 |
| V2 | rng_mode | entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 |
| V2 | rng_max_rate | entropy_src_rng_max_rate | 4.000s | 32.121us | 0 | 1 | 0.00 |
| V2 | health_checks | entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 |
| V2 | conditioning | entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 |
| V2 | interrupts | entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 |
| entropy_src_intr | 9.000s | 547.434us | 1 | 1 | 100.00 | ||
| V2 | alerts | entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 |
| entropy_src_functional_alerts | 5.000s | 58.589us | 1 | 1 | 100.00 | ||
| V2 | stress_all | entropy_src_stress_all | 2.767m | 11.231ms | 1 | 1 | 100.00 |
| V2 | functional_errors | entropy_src_functional_errors | 5.000s | 52.014us | 1 | 1 | 100.00 |
| V2 | firmware_ov_read_contiguous_data | entropy_src_fw_ov_contiguous | 13.000s | 1.449ms | 1 | 1 | 100.00 |
| V2 | intr_test | entropy_src_intr_test | 4.000s | 71.564us | 1 | 1 | 100.00 |
| V2 | alert_test | entropy_src_alert_test | 4.000s | 22.278us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | entropy_src_tl_errors | 6.000s | 453.907us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | entropy_src_tl_errors | 6.000s | 453.907us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | entropy_src_csr_hw_reset | 4.000s | 18.856us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 4.000s | 71.247us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 7.000s | 301.005us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 4.000s | 263.660us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | entropy_src_csr_hw_reset | 4.000s | 18.856us | 1 | 1 | 100.00 |
| entropy_src_csr_rw | 4.000s | 71.247us | 1 | 1 | 100.00 | ||
| entropy_src_csr_aliasing | 7.000s | 301.005us | 1 | 1 | 100.00 | ||
| entropy_src_same_csr_outstanding | 4.000s | 263.660us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 10 | 12 | 83.33 | |||
| V2S | tl_intg_err | entropy_src_sec_cm | 5.000s | 61.760us | 1 | 1 | 100.00 |
| entropy_src_tl_intg_err | 7.000s | 171.808us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_regwen | entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 |
| entropy_src_cfg_regwen | 4.000s | 41.970us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_config_mubi | entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 |
| V2S | sec_cm_config_redun | entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 |
| V2S | sec_cm_intersig_mubi | entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 |
| entropy_src_fw_ov | 1.917m | 13.025ms | 1 | 1 | 100.00 | ||
| V2S | sec_cm_main_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 52.014us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 61.760us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ack_sm_fsm_sparse | entropy_src_functional_errors | 5.000s | 52.014us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 61.760us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_rng_bkgn_chk | entropy_src_rng | 9.000s | 376.869us | 0 | 1 | 0.00 |
| V2S | sec_cm_fifo_ctr_redun | entropy_src_functional_errors | 5.000s | 52.014us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 61.760us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_redun | entropy_src_functional_errors | 5.000s | 52.014us | 1 | 1 | 100.00 |
| entropy_src_sec_cm | 5.000s | 61.760us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_ctr_local_esc | entropy_src_functional_errors | 5.000s | 52.014us | 1 | 1 | 100.00 |
| V2S | sec_cm_esfinal_rdata_bus_consistency | entropy_src_functional_alerts | 5.000s | 58.589us | 1 | 1 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | entropy_src_tl_intg_err | 7.000s | 171.808us | 1 | 1 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | external_health_tests | entropy_src_rng_with_xht_rsps | 35.000s | 1.879ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 19 | 22 | 86.36 |
UVM_ERROR (entropy_src_scoreboard.sv:2073) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: entropy_src_reg_block.recov_alert_sts has 2 failures:
Test entropy_src_rng has 1 failures.
0.entropy_src_rng.24430383680655072345718444650684007392913730820390226523315174207311386343139
Line 310, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng/latest/run.log
UVM_ERROR @ 376869102 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 376869102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test entropy_src_rng_with_xht_rsps has 1 failures.
0.entropy_src_rng_with_xht_rsps.38960496813476458849642419796145973163315858993903581737923547956177873482448
Line 930, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_with_xht_rsps/latest/run.log
UVM_ERROR @ 1879498070 ps: (entropy_src_scoreboard.sv:2073) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: entropy_src_reg_block.recov_alert_sts
UVM_INFO @ 1879498070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/fusesoc-work/src/lowrisc_fpv_entropy_src_csr_assert_*/entropy_src_csr_assert_fpv.sv,306): Assertion conf_rd_A has failed has 1 failures:
0.entropy_src_rng_max_rate.47948882335271270598332457803991551790273530644992134028486525662904415999629
Line 203, in log /nightly/runs/scratch/master/entropy_src-sim-xcelium/0.entropy_src_rng_max_rate/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/entropy_src-sim-xcelium/default/fusesoc-work/src/lowrisc_fpv_entropy_src_csr_assert_0/entropy_src_csr_assert_fpv.sv,306): (time 32121500 PS) Assertion tb.dut.entropy_src_csr_assert.conf_rd_A has failed
UVM_ERROR @ 32121500 ps: (entropy_src_csr_assert_fpv.sv:306) [ASSERT FAILED] conf_rd_A
UVM_INFO @ 32121500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---