HMAC Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 9.700s 5.389ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 2.030s 35.888us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.930s 14.749us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 5.230s 541.597us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.860s 314.376us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 4.016m 36.197ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.930s 14.749us 1 1 100.00
hmac_csr_aliasing 4.860s 314.376us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 19.140s 7.557ms 1 1 100.00
V2 back_pressure hmac_back_pressure 27.390s 7.049ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.210s 1.994ms 1 1 100.00
hmac_test_sha384_vectors 6.688m 58.845ms 1 1 100.00
hmac_test_sha512_vectors 19.570s 217.003us 1 1 100.00
hmac_test_hmac256_vectors 7.180s 155.383us 1 1 100.00
hmac_test_hmac384_vectors 8.110s 488.923us 1 1 100.00
hmac_test_hmac512_vectors 9.020s 981.414us 1 1 100.00
V2 burst_wr hmac_burst_wr 22.820s 3.916ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 8.670m 4.023ms 1 1 100.00
V2 error hmac_error 35.120s 3.689ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 26.820s 1.738ms 1 1 100.00
V2 save_and_restore hmac_smoke 9.700s 5.389ms 1 1 100.00
hmac_long_msg 19.140s 7.557ms 1 1 100.00
hmac_back_pressure 27.390s 7.049ms 1 1 100.00
hmac_datapath_stress 8.670m 4.023ms 1 1 100.00
hmac_burst_wr 22.820s 3.916ms 1 1 100.00
hmac_stress_all 2.738m 4.160ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 9.700s 5.389ms 1 1 100.00
hmac_long_msg 19.140s 7.557ms 1 1 100.00
hmac_back_pressure 27.390s 7.049ms 1 1 100.00
hmac_datapath_stress 8.670m 4.023ms 1 1 100.00
hmac_wipe_secret 26.820s 1.738ms 1 1 100.00
hmac_test_sha256_vectors 9.210s 1.994ms 1 1 100.00
hmac_test_sha384_vectors 6.688m 58.845ms 1 1 100.00
hmac_test_sha512_vectors 19.570s 217.003us 1 1 100.00
hmac_test_hmac256_vectors 7.180s 155.383us 1 1 100.00
hmac_test_hmac384_vectors 8.110s 488.923us 1 1 100.00
hmac_test_hmac512_vectors 9.020s 981.414us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 9.700s 5.389ms 1 1 100.00
hmac_long_msg 19.140s 7.557ms 1 1 100.00
hmac_back_pressure 27.390s 7.049ms 1 1 100.00
hmac_datapath_stress 8.670m 4.023ms 1 1 100.00
hmac_burst_wr 22.820s 3.916ms 1 1 100.00
hmac_error 35.120s 3.689ms 1 1 100.00
hmac_wipe_secret 26.820s 1.738ms 1 1 100.00
hmac_test_sha256_vectors 9.210s 1.994ms 1 1 100.00
hmac_test_sha384_vectors 6.688m 58.845ms 1 1 100.00
hmac_test_sha512_vectors 19.570s 217.003us 1 1 100.00
hmac_test_hmac256_vectors 7.180s 155.383us 1 1 100.00
hmac_test_hmac384_vectors 8.110s 488.923us 1 1 100.00
hmac_test_hmac512_vectors 9.020s 981.414us 1 1 100.00
hmac_stress_all 2.738m 4.160ms 1 1 100.00
V2 stress_all hmac_stress_all 2.738m 4.160ms 1 1 100.00
V2 alert_test hmac_alert_test 1.610s 12.215us 1 1 100.00
V2 intr_test hmac_intr_test 1.730s 50.634us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.280s 80.394us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.280s 80.394us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 2.030s 35.888us 1 1 100.00
hmac_csr_rw 1.930s 14.749us 1 1 100.00
hmac_csr_aliasing 4.860s 314.376us 1 1 100.00
hmac_same_csr_outstanding 2.460s 422.346us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 2.030s 35.888us 1 1 100.00
hmac_csr_rw 1.930s 14.749us 1 1 100.00
hmac_csr_aliasing 4.860s 314.376us 1 1 100.00
hmac_same_csr_outstanding 2.460s 422.346us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.020s 89.104us 1 1 100.00
hmac_tl_intg_err 3.310s 108.094us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.310s 108.094us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 9.700s 5.389ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.390s 508.801us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 47.460s 3.242ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.810s 28.603us 1 1 100.00
TOTAL 28 28 100.00