I2C Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: `952e1dd`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	16.060s	6.403ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	21.450s	1.961ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.560s	54.917us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.530s	37.324us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.610s	225.747us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.110s	67.468us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.960s	28.533us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.530s	37.324us	1	1	100.00
		i2c_csr_aliasing	2.110s	67.468us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.910s	743.892us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	12.305m	11.416ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	26.850s	12.743ms	1	1	100.00
V2	host_override	i2c_host_override	1.500s	45.929us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.940m	4.420ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	24.480s	2.792ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.060s	307.848us	1	1	100.00
		i2c_host_fifo_fmt_empty	8.610s	919.057us	1	1	100.00
		i2c_host_fifo_reset_rx	6.540s	602.556us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.599m	10.678ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	22.790s	2.730ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.520s	365.597us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.790s	1.887ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.422m	35.307ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.690s	654.172us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	21.670s	7.597ms	1	1	100.00
		i2c_target_intr_smoke	5.930s	12.403ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.020s	397.045us	1	1	100.00
		i2c_target_fifo_reset_tx	1.970s	642.421us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	11.980s	10.469ms	1	1	100.00
		i2c_target_stress_rd	21.670s	7.597ms	1	1	100.00
		i2c_target_intr_stress_wr	14.150s	10.331ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.550s	11.258ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	9.530s	961.309us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.870s	444.848us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	5.790s	10.021ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.880s	1.969ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.020s	151.637us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	26.850s	12.743ms	1	1	100.00
		i2c_host_perf_precise	1.980s	53.561us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	22.790s	2.730ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.550s	102.964us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.000s	2.386ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.570s	432.555us	1	1	100.00
		i2c_target_nack_txstretch	2.100s	511.404us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	15.550s	555.075us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.500s	1.697ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.550s	43.949us	1	1	100.00
V2	intr_test	i2c_intr_test	1.520s	20.901us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.430s	117.260us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.430s	117.260us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.560s	54.917us	1	1	100.00
		i2c_csr_rw	1.530s	37.324us	1	1	100.00
		i2c_csr_aliasing	2.110s	67.468us	1	1	100.00
		i2c_same_csr_outstanding	1.590s	54.558us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.560s	54.917us	1	1	100.00
		i2c_csr_rw	1.530s	37.324us	1	1	100.00
		i2c_csr_aliasing	2.110s	67.468us	1	1	100.00
		i2c_same_csr_outstanding	1.590s	54.558us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.600s	91.973us	1	1	100.00
		i2c_sec_cm	1.710s	69.126us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.600s	91.973us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.210s	455.391us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.030s	191.552us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.100s	2.105ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.94997983086664044346727654405742766131763890270437513808896030633605179736529
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 191552190 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 191552190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.8597503255176145775622189472934981375126475482010085525406048439512187435123
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10021400514 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10021400514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.71844210395829051686785814111387323191796084171857847411299235093413896350186
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 455391456 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 455391456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.114436103864858280712361914336851491824505288860305085088659685239661581218973
    Line 125, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2105476219 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 238 [0xee])
  UVM_INFO @ 2105476219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.16292872331375169651629272403060264290639870132298080938348977404631313556152
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 365596959 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @10361