KEYMGR Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.600s	270.563us	1	1	100.00
V1	random	keymgr_random	4.040s	181.803us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.530s	20.274us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.180s	18.484us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.090s	137.816us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.550s	1.394ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.870s	24.419us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.180s	18.484us	1	1	100.00
		keymgr_csr_aliasing	6.550s	1.394ms	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	5.540s	114.888us	1	1	100.00
V2	sideload	keymgr_sideload	4.070s	185.688us	1	1	100.00
		keymgr_sideload_kmac	3.050s	56.451us	1	1	100.00
		keymgr_sideload_aes	2.950s	941.322us	1	1	100.00
		keymgr_sideload_otbn	4.750s	802.605us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.000s	119.949us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.060s	82.968us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.740s	84.835us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.330s	466.136us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.330s	94.241us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.950s	121.512us	1	1	100.00
V2	stress_all	keymgr_stress_all	5.010s	239.896us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.460s	41.439us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.750s	18.094us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.170s	479.700us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.170s	479.700us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.530s	20.274us	1	1	100.00
		keymgr_csr_rw	2.180s	18.484us	1	1	100.00
		keymgr_csr_aliasing	6.550s	1.394ms	1	1	100.00
		keymgr_same_csr_outstanding	2.880s	479.578us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.530s	20.274us	1	1	100.00
		keymgr_csr_rw	2.180s	18.484us	1	1	100.00
		keymgr_csr_aliasing	6.550s	1.394ms	1	1	100.00
		keymgr_same_csr_outstanding	2.880s	479.578us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
		keymgr_tl_intg_err	4.070s	109.387us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.380s	76.003us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.380s	76.003us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.380s	76.003us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.380s	76.003us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.240s	183.152us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.070s	109.387us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.380s	76.003us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	5.540s	114.888us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	4.040s	181.803us	1	1	100.00
		keymgr_csr_rw	2.180s	18.484us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	4.040s	181.803us	1	1	100.00
		keymgr_csr_rw	2.180s	18.484us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	4.040s	181.803us	1	1	100.00
		keymgr_csr_rw	2.180s	18.484us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.060s	82.968us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.330s	94.241us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.330s	94.241us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	4.040s	181.803us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.600s	83.674us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.840s	49.827us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.060s	82.968us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.840s	49.827us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.840s	49.827us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.840s	49.827us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.070s	711.737us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.840s	49.827us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	15.280s	2.836ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.63219299240041387877962064325846834831076268707156424663412818136335901595246
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @  24419083 ps: (keymgr_csr_assert_fpv.sv:484) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @  24419083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---