KMAC/MASKED Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	45.420s	4.421ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.900s	30.252us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.930s	33.073us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.100s	2.874ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.080s	504.036us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.750s	49.239us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.930s	33.073us	1	1	100.00
		kmac_csr_aliasing	6.080s	504.036us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.660s	17.697us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.160s	20.757us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.071m	891.869us	1	1	100.00
V2	burst_write	kmac_burst_write	4.162m	18.164ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.653m	444.313ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.550s	2.211ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.224m	88.975ms	1	1	100.00
		kmac_test_vectors_sha3_512	21.450s	23.213ms	1	1	100.00
		kmac_test_vectors_shake_128	36.335m	1.334s	1	1	100.00
		kmac_test_vectors_shake_256	4.771m	11.151ms	1	1	100.00
		kmac_test_vectors_kmac	3.160s	217.031us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.890s	75.194us	1	1	100.00
V2	sideload	kmac_sideload	4.120m	44.738ms	1	1	100.00
V2	app	kmac_app	2.275m	7.638ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.306m	8.996ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.832m	37.530ms	1	1	100.00
V2	error	kmac_error	10.670s	323.757us	1	1	100.00
V2	key_error	kmac_key_error	6.640s	1.988ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	6.340s	215.063us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.890s	69.781us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	26.760s	921.769us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	47.610s	6.402ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.750s	63.360us	1	1	100.00
V2	stress_all	kmac_stress_all	35.475m	93.399ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.690s	23.458us	1	1	100.00
V2	alert_test	kmac_alert_test	1.530s	82.321us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.750s	263.835us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.750s	263.835us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.900s	30.252us	1	1	100.00
		kmac_csr_rw	1.930s	33.073us	1	1	100.00
		kmac_csr_aliasing	6.080s	504.036us	1	1	100.00
		kmac_same_csr_outstanding	2.870s	130.560us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.900s	30.252us	1	1	100.00
		kmac_csr_rw	1.930s	33.073us	1	1	100.00
		kmac_csr_aliasing	6.080s	504.036us	1	1	100.00
		kmac_same_csr_outstanding	2.870s	130.560us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.310s	126.345us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.310s	126.345us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.310s	126.345us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.310s	126.345us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.110s	59.369us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	50.400s	4.935ms	1	1	100.00
		kmac_tl_intg_err	3.930s	113.801us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.930s	113.801us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.750s	63.360us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	45.420s	4.421ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.120m	44.738ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.310s	126.345us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	50.400s	4.935ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	50.400s	4.935ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	50.400s	4.935ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	45.420s	4.421ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.750s	63.360us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	50.400s	4.935ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	59.800s	1.664ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	45.420s	4.421ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	28.590s	1.987ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.72331805535330341175233747866763227846982430618657567075559420061931417391340
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  59368979 ps: (kmac_csr_assert_fpv.sv:524) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  59368979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---