KMAC/UNMASKED Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: `952e1dd`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	21.470s	1.273ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.030s	71.249us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.710s	28.557us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.700s	309.652us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.330s	389.451us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.730s	653.668us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.710s	28.557us	1	1	100.00
		kmac_csr_aliasing	4.330s	389.451us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.520s	12.382us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.030s	115.528us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	41.927m	534.986ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.705m	12.636ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	18.845m	36.713ms	1	1	100.00
		kmac_test_vectors_sha3_256	22.370s	1.900ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.160s	6.897ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.800s	3.291ms	1	1	100.00
		kmac_test_vectors_shake_128	21.671m	85.656ms	1	1	100.00
		kmac_test_vectors_shake_256	16.692m	33.708ms	1	1	100.00
		kmac_test_vectors_kmac	2.910s	806.311us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.450s	47.481us	1	1	100.00
V2	sideload	kmac_sideload	31.530s	1.704ms	1	1	100.00
V2	app	kmac_app	47.190s	25.093ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.462m	43.325ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.360s	498.554us	1	1	100.00
V2	error	kmac_error	37.580s	2.062ms	1	1	100.00
V2	key_error	kmac_key_error	6.750s	7.515ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.380s	60.202us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	11.200s	247.438us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	16.740s	1.236ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	18.510s	2.402ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.380s	38.342us	1	1	100.00
V2	stress_all	kmac_stress_all	14.204m	85.197ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.630s	33.538us	1	1	100.00
V2	alert_test	kmac_alert_test	1.540s	23.248us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.010s	583.969us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.010s	583.969us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.030s	71.249us	1	1	100.00
		kmac_csr_rw	1.710s	28.557us	1	1	100.00
		kmac_csr_aliasing	4.330s	389.451us	1	1	100.00
		kmac_same_csr_outstanding	3.110s	153.305us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.030s	71.249us	1	1	100.00
		kmac_csr_rw	1.710s	28.557us	1	1	100.00
		kmac_csr_aliasing	4.330s	389.451us	1	1	100.00
		kmac_same_csr_outstanding	3.110s	153.305us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.200s	32.041us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.200s	32.041us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.200s	32.041us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.200s	32.041us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.970s	42.147us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	19.580s	2.517ms	1	1	100.00
		kmac_tl_intg_err	1.710s	21.168us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.710s	21.168us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.380s	38.342us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	21.470s	1.273ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	31.530s	1.704ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.200s	32.041us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	19.580s	2.517ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	19.580s	2.517ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	19.580s	2.517ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	21.470s	1.273ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.380s	38.342us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	19.580s	2.517ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	19.820s	10.414ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	21.470s	1.273ms	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	17.010s	3.346ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			37	40	92.50

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

0.kmac_shadow_reg_errors_with_csr_rw.17995086067798155363428247095095623328795275855142713393516984479493765224821
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  42147189 ps: (kmac_csr_assert_fpv.sv:530) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  42147189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_tl_intg_err has 1 failures.

0.kmac_tl_intg_err.46772572491824688656796162799033230108848194971001682727771890452598262916104
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  21168181 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  21168181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 0.kmac_stress_all_with_rand_reset.56736273208610747884371963565221896486803764209465362363582132175910328669917
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3346373382 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3346373382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```