OTBN Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	10.000s	77.545us	1	1	100.00
V1	single_binary	otbn_single	19.000s	109.956us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	5.000s	66.745us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	49.647us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	6.000s	83.116us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	5.000s	47.685us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	6.000s	71.950us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	49.647us	1	1	100.00
		otbn_csr_aliasing	5.000s	47.685us	1	1	100.00
V1	mem_walk	otbn_mem_walk	26.000s	1.781ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	10.000s	731.065us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	26.000s	81.757us	1	1	100.00
V2	multi_error	otbn_multi_err	44.000s	658.237us	1	1	100.00
V2	back_to_back	otbn_multi	45.000s	150.608us	1	1	100.00
V2	stress_all	otbn_stress_all	40.000s	419.238us	1	1	100.00
V2	lc_escalation	otbn_escalate	9.000s	227.393us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	38.857us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	10.000s	15.842us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	15.371us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	31.056us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	8.000s	54.969us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	8.000s	54.969us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	5.000s	66.745us	1	1	100.00
		otbn_csr_rw	6.000s	49.647us	1	1	100.00
		otbn_csr_aliasing	5.000s	47.685us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	15.707us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	5.000s	66.745us	1	1	100.00
		otbn_csr_rw	6.000s	49.647us	1	1	100.00
		otbn_csr_aliasing	5.000s	47.685us	1	1	100.00
		otbn_same_csr_outstanding	5.000s	15.707us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	9.000s	16.830us	1	1	100.00
		otbn_dmem_err	10.000s	18.557us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	18.000s	69.265us	1	1	100.00
		otbn_controller_ispr_rdata_err	35.000s	211.375us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	129.026us	1	1	100.00
		otbn_urnd_err	8.000s	24.788us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	7.000s	10.040us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	19.159us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	6.000s	14.820us	0	1	0.00
V2S	tl_intg_err	otbn_sec_cm	6.000s	6.497us	0	1	0.00
		otbn_tl_intg_err	16.000s	480.220us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	22.000s	382.711us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	10.000s	77.545us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	10.000s	18.557us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	16.830us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	16.000s	480.220us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	9.000s	227.393us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	16.830us	1	1	100.00
		otbn_dmem_err	10.000s	18.557us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	38.857us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	10.040us	1	1	100.00
		otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	19.000s	109.956us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	16.830us	1	1	100.00
		otbn_dmem_err	10.000s	18.557us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	38.857us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	10.040us	1	1	100.00
		otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	9.000s	227.393us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	16.830us	1	1	100.00
		otbn_dmem_err	10.000s	18.557us	1	1	100.00
		otbn_zero_state_err_urnd	9.000s	38.857us	1	1	100.00
		otbn_illegal_mem_acc	7.000s	10.040us	1	1	100.00
		otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	19.000s	109.956us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	23.734us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	10.000s	39.071us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	27.000s	190.508us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	27.000s	190.508us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	9.000s	89.852us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	15.000s	283.097us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	107.735us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	107.735us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	6.000s	15.729us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	19.000s	109.956us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	19.000s	109.956us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	19.000s	109.956us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	45.000s	150.608us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	19.000s	109.956us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	19.000s	109.956us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	9.000s	32.120us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	19.000s	109.956us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.000s	6.497us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.767m	4.236ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	41	92.68

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.103472361544870683079500360160034460105236801826735381954838800597665853310821
      Line 349, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4236418765 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4236418765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:

  • Test otbn_partial_wipe has 1 failures.

    • 0.otbn_partial_wipe.56515833685153114565403882738172143100611620328892765443752189206956168057873
      Line 108, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_partial_wipe/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 14819897 PS) Assertion tb.MatchingStatus_A has failed
        UVM_ERROR @  14819897 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
        UVM_INFO @  14819897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.67067813122467991197877530161628029017913942081298194273553631659576158804623
      Line 88, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 6496754 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 6496754 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @   6496754 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @   6496754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---