952e1dd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 5.000s | 57.853us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 5.000s | 73.453us | 1 | 1 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 4.000s | 39.803us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 5.000s | 193.391us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 4.000s | 51.930us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 4.000s | 29.085us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 4.000s | 39.803us | 1 | 1 | 100.00 |
| pattgen_csr_aliasing | 4.000s | 51.930us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | perf | pattgen_perf | 31.183m | 600.000ms | 0 | 1 | 0.00 |
| V2 | cnt_rollover | cnt_rollover | 7.000s | 2.146ms | 1 | 1 | 100.00 |
| V2 | error | pattgen_error | 4.000s | 17.340us | 1 | 1 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 5.000s | 169.477us | 0 | 1 | 0.00 |
| V2 | alert_test | pattgen_alert_test | 4.000s | 44.079us | 1 | 1 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 4.000s | 55.628us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 5.000s | 99.022us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 5.000s | 99.022us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 5.000s | 73.453us | 1 | 1 | 100.00 |
| pattgen_csr_rw | 4.000s | 39.803us | 1 | 1 | 100.00 | ||
| pattgen_csr_aliasing | 4.000s | 51.930us | 1 | 1 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 14.557us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 5.000s | 73.453us | 1 | 1 | 100.00 |
| pattgen_csr_rw | 4.000s | 39.803us | 1 | 1 | 100.00 | ||
| pattgen_csr_aliasing | 4.000s | 51.930us | 1 | 1 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 14.557us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 6 | 8 | 75.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 4.000s | 52.613us | 1 | 1 | 100.00 |
| pattgen_sec_cm | 4.000s | 163.001us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 4.000s | 52.613us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 21.000s | 9.178ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | pattgen_inactive_level | 3.983m | 10.006ms | 0 | 1 | 0.00 | |
| TOTAL | 14 | 18 | 77.78 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
0.pattgen_perf.79473070644647478239895171959698945710284064845330850118910586082767823696293
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
0.pattgen_inactive_level.22502253111191187222229480263337996703325484825224416342203938479773895432425
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10006307748 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa8540590, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10006307748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:929) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.pattgen_stress_all_with_rand_reset.39044435800371443117538048832450503726733146362420081234595714202467242313288
Line 110, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 453691596 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 453733189 ps: (cip_base_vseq.sv:833) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 453733189 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 454149859 ps: (cip_base_vseq.sv:857) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
0.pattgen_stress_all.62677756636846554333915134181679966048136929992320860590809252709789338278514
Line 145, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 169476828 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10578