ROM_CTRL/64KB Simulation Results

Wednesday June 18 2025 18:31:46 UTC

GitHub Revision: 952e1dd

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.570s 389.497us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.400s 1.427ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.650s 1.025ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.670s 1.691ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.680s 292.916us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.350s 1.137ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.650s 1.025ms 1 1 100.00
rom_ctrl_csr_aliasing 7.680s 292.916us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.610s 543.942us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.990s 209.997us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.050s 4.292ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 28.910s 1.319ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 16.280s 1.082ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.200s 297.273us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.460s 2.391ms 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.460s 2.391ms 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.400s 1.427ms 1 1 100.00
rom_ctrl_csr_rw 6.650s 1.025ms 1 1 100.00
rom_ctrl_csr_aliasing 7.680s 292.916us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.250s 299.740us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.400s 1.427ms 1 1 100.00
rom_ctrl_csr_rw 6.650s 1.025ms 1 1 100.00
rom_ctrl_csr_aliasing 7.680s 292.916us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.250s 299.740us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.600m 8.133ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 37.080s 6.361ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.783m 1.297ms 1 1 100.00
rom_ctrl_tl_intg_err 1.030m 1.578ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.783m 1.297ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 4.783m 1.297ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.600m 8.133ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.600m 8.133ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.600m 8.133ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.600m 8.133ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.600m 8.133ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.783m 1.297ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.783m 1.297ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.570s 389.497us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.570s 389.497us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.570s 389.497us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.030m 1.578ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.600m 8.133ms 1 1 100.00
rom_ctrl_kmac_err_chk 16.280s 1.082ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.600m 8.133ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.600m 8.133ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.600m 8.133ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 37.080s 6.361ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.783m 1.297ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.142m 4.532ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00